US6087707A
Expired / Lapsed
US
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Structure for an antifuse cell
Assignee: Micron Technology Inc
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Filing: 1996-04-16
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Granted: 2000-07-11
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Expires: 2016-04-16
Abstract
Abstract A structure for an antifuse cell which comprises: (a) field oxide between the bottom plate of the antifuse element and its access transistor; and (b) an implanted region underlying the antifuse element to provide a conductive path between the source of the access transistor and the antifuse element.
Inventors
- 👤 Roger Lee
- 👤 Fernando Gonzalez
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 02:37
CPC Classifications
H; H10; H10B; H10B20/00; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
145 words
An antifuse cell for an integrated circuit, the antifuse cell comprising: an access device formed on a substrate, the access device having a first doped region; a field oxide region formed on the substrate adjacent the access device; and an antifuse formed on the substrate adjacent the field oxide region, the field oxide region being disposed between the access device and the antifuse, the antifuse having a second doped region, a third doped region, a programmable layer, and a conductive layer, the second doped region forming a bottom plate of the antifuse, the third doped region disposed beneath the entire second doped region and extending under the field oxide region and being coupled to the first doped region, the programmable layer being disposed over the second doped region and terminating above the field oxide region, and the conductive layer being disposed over the programmable layer.
Claim 2
Dependent Claim
145 words
An antifuse cell for an integrated circuit, the antifuse cell comprising: an access device formed on a substrate, the access device having a first doped region; a field oxide region formed on the substrate adjacent the access device; and an antifuse formed on the substrate adjacent the field oxide region, the field oxide region being disposed between the access device and the antifuse, the antifuse having a second doped region, a third doped region, a programmable layer, and a conductive layer, the second doped region forming a bottom plate of the antifuse, the third doped region disposed beneath the entire second doped region and extending under the field oxide region and being coupled to the first doped region, the programmable layer being disposed over the second doped region and terminating above the field oxide region, and the conductive layer being disposed over the programmable layer.
Claim 3
Dependent Claim
16 words
The antifuse cell, as set forth in claim 1, wherein the programmable layer comprises dielectric material.
Claim 4
Dependent Claim
17 words
The antifuse cell, as set forth in claim 2, wherein the dielectric material comprises an ONO structure.
Claim 5
Dependent Claim
16 words
The antifuse cell, as set forth in claim 1, wherein the programmable layer comprises amorphous silicon.
Claim 6
Dependent Claim
22 words
The antifuse cell, as set forth in claim 1, wherein the first doped region and the second doped region are N doped.
Claim 7
Dependent Claim
15 words
The antifuse cell, as set forth in claim 1, wherein the conductive layer comprises polysilicon.
Claim 8
Dependent Claim
126 words
An antifuse cell for an integrated circuit, the antifuse cell comprising: an access device formed on a substrate, the access device having a first doped region; a field oxide region formed on the substrate adjacent the access device; an antifuse formed on the substrate adjacent the field oxide region, the field oxide region being disposed between the access device and the antifuse, the antifuse having a bottom plate, a programmable layer disposed over the bottom plate, and a top plate disposed over the programmable layer, the programmable layer and the top plate terminating above the field oxide region; and a second doped region formed beneath the entire bottom plate and extending under the field oxide region to couple the first doped region to the bottom plate.
Claim 9
Dependent Claim
126 words
An antifuse cell for an integrated circuit, the antifuse cell comprising: an access device formed on a substrate, the access device having a first doped region; a field oxide region formed on the substrate adjacent the access device; an antifuse formed on the substrate adjacent the field oxide region, the field oxide region being disposed between the access device and the antifuse, the antifuse having a bottom plate, a programmable layer disposed over the bottom plate, and a top plate disposed over the programmable layer, the programmable layer and the top plate terminating above the field oxide region; and a second doped region formed beneath the entire bottom plate and extending under the field oxide region to couple the first doped region to the bottom plate.
Claim 10
Dependent Claim
16 words
The antifuse cell, as set forth in claim 7, wherein the programmable layer comprises dielectric material.
Claim 11
Dependent Claim
17 words
The antifuse cell, as set forth in claim 8, wherein the dielectric material comprises an ONO structure.
Claim 12
Dependent Claim
16 words
The antifuse cell, as set forth in claim 7, wherein the programmable layer comprises amorphous silicon.
Claim 13
Dependent Claim
21 words
The antifuse cell, as set forth in claim 7, wherein the first doped region and the bottom plate are N+ doped.
Claim 14
Dependent Claim
17 words
The antifuse cell, as set forth in claim 7, wherein the second doped region is N- doped.
Claim 15
Dependent Claim
15 words
The antifuse cell, as set forth in claim 7, wherein the top plate comprises polysilicon.
Claim 16
Dependent Claim
158 words
An integrated circuit memory device comprising: a memory array comprising a plurality of memory cells, at least a portion of the memory cells comprising: an access device formed on a substrate, the access device having a first doped region; a field oxide region formed on the substrate adjacent the access device; and an antifuse formed on the substrate adjacent the field oxide region, the field oxide region being disposed between the access device and the antifuse, the antifuse having a second doped region, a third doped region, a programmable layer, and a conductive layer, the second doped region forming a bottom plate of the antifuse, the third doped region disposed beneath the entire second doped region and extending under the field oxide region and being coupled to the first doped region, the programmable layer being disposed over the second doped region and terminating above the field oxide region, and the conductive layer being disposed over the programmable layer.
Claim 17
Dependent Claim
158 words
An integrated circuit memory device comprising: a memory array comprising a plurality of memory cells, at least a portion of the memory cells comprising: an access device formed on a substrate, the access device having a first doped region; a field oxide region formed on the substrate adjacent the access device; and an antifuse formed on the substrate adjacent the field oxide region, the field oxide region being disposed between the access device and the antifuse, the antifuse having a second doped region, a third doped region, a programmable layer, and a conductive layer, the second doped region forming a bottom plate of the antifuse, the third doped region disposed beneath the entire second doped region and extending under the field oxide region and being coupled to the first doped region, the programmable layer being disposed over the second doped region and terminating above the field oxide region, and the conductive layer being disposed over the programmable layer.
Claim 18
Dependent Claim
16 words
The memory device, as set forth in claim 14, wherein the programmable layer comprises dielectric material.
Claim 19
Dependent Claim
17 words
The memory device, as set forth in claim 15, wherein the dielectric material comprises an ONO structure.
Claim 20
Dependent Claim
16 words
The memory device, as set forth in claim 14, wherein the programmable layer comprises amorphous silicon.
Claim 21
Dependent Claim
22 words
The memory device, as set forth in claim 14, wherein the first doped region and the second doped region are N doped.
Claim 22
Dependent Claim
15 words
The memory device, as set forth in claim 14, wherein the conductive layer comprises polysilicon.
Claim 23
Dependent Claim
139 words
An integrated circuit memory device comprising: a memory array comprising a plurality of memory cells, at least a portion of the memory cells comprising: an access device formed on a substrate, the access device having a first doped region; a field oxide region formed on the substrate adjacent the access device; an antifuse formed on the substrate adjacent the field oxide region, the field oxide region being disposed between the access device and the antifuse, the antifuse having a bottom plate, a programmable layer disposed over the bottom plate, and a top plate disposed over the programmable layer, the programmable layer and the top plate terminating above the field oxide region; and a second doped region formed beneath the entire bottom plate and extending under the field oxide region to couple the first doped region to the bottom plate.
Claim 24
Dependent Claim
139 words
An integrated circuit memory device comprising: a memory array comprising a plurality of memory cells, at least a portion of the memory cells comprising: an access device formed on a substrate, the access device having a first doped region; a field oxide region formed on the substrate adjacent the access device; an antifuse formed on the substrate adjacent the field oxide region, the field oxide region being disposed between the access device and the antifuse, the antifuse having a bottom plate, a programmable layer disposed over the bottom plate, and a top plate disposed over the programmable layer, the programmable layer and the top plate terminating above the field oxide region; and a second doped region formed beneath the entire bottom plate and extending under the field oxide region to couple the first doped region to the bottom plate.
Claim 25
Dependent Claim
16 words
The memory device, as set forth in claim 20, wherein the programmable layer comprises dielectric material.
Claim 26
Dependent Claim
17 words
The memory device, as set forth in claim 21, wherein the dielectric material comprises an ONO structure.
Claim 27
Dependent Claim
16 words
The memory device, as set forth in claim 20, wherein the programmable layer comprises amorphous silicon.
Claim 28
Dependent Claim
21 words
The memory device, as set forth in claim 20, wherein the first doped region and the bottom plate are N+ doped.
Claim 29
Dependent Claim
17 words
The memory device, as set forth in claim 20, wherein the second doped region is N- doped.
Claim 30
Dependent Claim
15 words
The memory device, as set forth in claim 20, wherein the top plate comprises polysilicon.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-11 | 2004-01-10 | 2004-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-11 | 2008-01-10 | 2008-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-11 | 2012-01-10 | 2012-07-11 | $7700.00 | Window Closed / Lapsed |