System and method for an antifuse bank

Claim 2

An antifuse bank for an integrated circuit, the antifuse bank comprising: a plurality of word and digit lines disposed to form an array; a plurality of antifuse cells, each antifuse cell including: an antifuse that is programmable from a first state to a second state; an access device coupled to one of the word lines and one of the digit lines and coupled to the antifuse; an addressing circuit coupled to the array that selects an antifuse of the array to be accessed; a sensing circuit coupled to the array that senses the state of the selected antifuse; and wherein the antifuse of each antifuse cell comprises a capacitive element, wherein the capacitance of the capacitive element does not exceed 25 nanofarads.

Claim 5

A memory device, comprising: an array of storage cells for storing data for the memory device; an address decoder coupled to the array of storage cells that selects a cell of the array to be accessed; and an array of antifuses that is coupled to provide data to the address decoder for use in selecting cells of the array of storage cells.

Claim 6

A memory device, comprising: an array of storage cells for storing data for the memory device; an address decoder coupled to the array of storage cells that selects a cell of the array to be accessed; and an array of antifuses that is coupled to provide data to the address decoder for use in selecting cells of the array of storage cells.

Claim 7

A memory device, comprising: an array of storage cells for storing data for the memory device; an address decoder that is coupled to the array of storage cells to selectively access storage cells of the array; and an antifuse bank that is coupled to provide data to the address decoder for use in selecting storage cells of the array of storage cells, wherein the antifuse bank comprises: a plurality of word and digit lines disposed to form an array, a plurality of antifuse cells, each antifuse cell including: an antifuse that is programmable to one of two states, an access device coupled to one of the word lines and one of the digit lines and coupled to the antifuse, a word decoder and a digit decoder that are coupled to the word and digit lines that selects an antifuse of the array to be accessed, and a sensing circuit coupled to the digit lines that senses the state of the selected antifuse, wherein each sensing circuit comprises at least one transistor that is coupled to one of the digit lines to impose a first voltage on the digit line, wherein an antifuse cell coupled to the digit line overcomes the effect of the at least one transistor during a read operation when the antifuse of the cell is in a first state, thus producing a second voltage on the digit line.

Claim 8

A memory device, comprising: an array of storage cells for storing data for the memory device; an address decoder that is coupled to the array of storage cells to selectively access storage cells of the array; and an antifuse bank that is coupled to provide data to the address decoder for use in selecting storage cells of the array of storage cells, wherein the antifuse bank comprises: a plurality of word and digit lines disposed to form an array, a plurality of antifuse cells, each antifuse cell including: an antifuse that is programmable to one of two states, an access device coupled to one of the word lines and one of the digit lines and coupled to the antifuse, a word decoder and a digit decoder that are coupled to the word and digit lines that selects an antifuse of the array to be accessed, and a sensing circuit coupled to the digit lines that senses the state of the selected antifuse, wherein each sensing circuit comprises at least one transistor that is coupled to one of the digit lines to impose a first voltage on the digit line, wherein an antifuse cell coupled to the digit line overcomes the effect of the at least one transistor during a read operation when the antifuse of the cell is in a first state, thus producing a second voltage on the digit line.

Claim 9

The memory device of claim 4, wherein the antifuse of each antifuse cell is coupled to a common node.

Claim 10

The memory device of claim 4, wherein the at least one transistor of the sensing circuit is a long L device, such that the effect of the at least one transistor on the voltage of the digit line can be overcome by an antifuse cell.

Claim 11

The memory device of claim 4, wherein a sensing circuit is coupled to each digit line.

Claim 12

The memory device of claim 4, wherein the antifuse of each antifuse cell comprises a capacitive element, wherein the capacitance of the capacitive element does not exceed 25 nanofarads.

Claim 13

A memory device, comprising: an array of storage cells for storing data for the memory device; an address decoder that is coupled to the array of storage cells to selectively access storage cells of the array; and an antifuse bank that is coupled to provide data to the address decoder for use in selecting storage cells of the array of storage cells, wherein the antifuse bank comprises: a plurality of word and digit lines disposed to form an array, a cell plate, a plurality of antifuse cells, each antifuse cell including: an access device coupled to one of the word lines and one of the digit lines, and an antifuse that is programmable from a first state to a second state, the antifuse having a first node coupled to the access device and a second node coupled to the cell plate, a word decoder and a digit decoder coupled to the array that selects an antifuse of the array to be accessed, and a sensing circuit coupled to the array that senses a voltage that indicates the state of the selected antifuse.

Claim 14

A memory device, comprising: an array of storage cells for storing data for the memory device; an address decoder that is coupled to the array of storage cells to selectively access storage cells of the array; and an antifuse bank that is coupled to provide data to the address decoder for use in selecting storage cells of the array of storage cells, wherein the antifuse bank comprises: a plurality of word and digit lines disposed to form an array, a cell plate, a plurality of antifuse cells, each antifuse cell including: an access device coupled to one of the word lines and one of the digit lines, and an antifuse that is programmable from a first state to a second state, the antifuse having a first node coupled to the access device and a second node coupled to the cell plate, a word decoder and a digit decoder coupled to the array that selects an antifuse of the array to be accessed, and a sensing circuit coupled to the array that senses a voltage that indicates the state of the selected antifuse.

Claim 15

The memory device of claim 9, wherein a sensing circuit is coupled to each digit line.

Claim 16

The memory device of claim 9, wherein each antifuse associated wit a common digit line is programmed to the same state.

Claim 17

The memory device of claim 9, wherein the antifuse of each antifuse cell comprises a capacitive element, wherein the capacitance of the capacitive element does not exceed 25 nanofarads.

Claim 20

The method of claim 13, wherein establishing the high voltage on the digit line comprises establishing a high voltage on the digit line with a circuit that includes at least one long L device.

Claim 21

The method of claim 13, wherein establishing the high voltage on the digit line comprises: providing a control signal with a first voltage level to a long L device to establish the high voltage on the digit line; and adjusting the control signal to a second, different voltage level to turn off the long L device to allow the voltage on the digit line to be changed by the selected cell.

Claim 24

The method of claim 16, wherein monitoring the voltage on the digit lines comprises determining whether the digit line has a high logic level or a low logic level.

Claim 25

The method of claim 16, wherein identifying defective cells comprises identifying cells that drive the digit line to a low logic level.

Claim 26

The method of claim 16, and further comprising isolating the defective cells during normal operation.

Claim 27

The method of claim 19, wherein isolating the defective cells comprises grounding word lines associated with the defective cells during normal operation.