On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same

Claim 1

A programmable non-volatile memory device comprising: a memory array of addressable memory cells for storing electronic data; multiple redundant memory cells for replacing defective memory cells in the memory array; an address buffer coupled to the memory array for holding a selected address to one or more memory cells in the memory array; a data buffer coupled to the memory array for holding data to be input into the memory cells at the selected address; a controller for initiating a programming cycle to program the memory array, one programming cycle including accessing the memory array at the selected address held in the address buffer and writing the data held in the data buffer into the memory cells at the selected address; the controller, in the event that the data is not validly written into the addressed memory cells, repeatedly initiating the programming cycle for the addressed memory cells in an attempt to validly write the data into the addressed memory cells within the memory array; a counter for counting a number of programming cycles that the controller initiates to the same address, the counter outputting a redundancy enable signal when the number of programming cycles reaches a predetermined number indicating that the addressed memory cells are defective; a redundancy address matching circuit operatively coupled to the counter and the address buffer for managing the replacement of defective memory cells in the memory array with the redundant memory cells, the redundancy address matching circuit assigning the redundant memory cells for the defective memory cells upon receipt of the redundancy enable signal from the counter; and the memory device subsequently routing the data to the redundant memory cells instead of the defective memory cells.

Claim 20

A system for testing a programmable non-volatile memory device to identify and disable defective memory cells, the system comprising: the programmable non-volatile memory device having a memory array of addressable memory cells for storing electronic data and multiple redundant memory cells for replacing defective memory cells in the memory array; a programming device for programming the programmable non-volatile memory device and for subsequently monitoring the memory device to determine whether the memory device has been validly programmed; the programming device operating according to an algorithm for programming individual memory cells in the memory device where in the event that the memory cells are not validly programmed, the programming device continues to program the same memory cells for a predetermined number of programming attempts in an effort to validly program the memory cells; the programmable non-volatile memory device further comprising: an address buffer coupled to the memory array for holding a selected address to one or more memory cells in the memory array; a data buffer coupled to the memory array for holding data to be input into the memory cells at the selected address; a controller for initiating an internal programming cycle to program the memory array in response the programming attempts made by the programming device, the internal programming cycle including accessing the memory array at the selected address held in the address buffer and writing the data held in the data buffer into the memory cells at the selected address; the controller, in the event that the data is not validly written into the addressed memory cells, repeatedly initiating the programming cycle for the same addressed memory cells in response to the continued programming attempts made by the programming device; a counter for counting a number of internal programming cycles that the controller initiates to the same address, the counter outputting a redundancy enable signal when the number of programming cycles reaches a predetermined number indicating that the addressed memory cells are defective, the predetermined number of internal programming cycles being less than or equal to the predetermined number of programming attempts; a redundancy address matching circuit operatively coupled to the counter and the address buffer for managing the replacement of defective memory cells in the memory array with the redundant memory cells, the redundancy address matching circuit assigning the redundant memory cells for the defective memory cells upon receipt of the redundancy enable signal from the counter; and the memory device subsequently routing the data to the redundant memory cells instead of the defective memory cells.

Claim 21

A system for testing a programmable non-volatile memory device to identify and disable defective memory cells, the system comprising: the programmable non-volatile memory device having a memory array of addressable memory cells for storing electronic data and multiple redundant memory cells for replacing defective memory cells in the memory array; a programming device for programming the programmable non-volatile memory device and for subsequently monitoring the memory device to determine whether the memory device has been validly programmed; the programming device operating according to an algorithm for programming individual memory cells in the memory device where in the event that the memory cells are not validly programmed, the programming device continues to program the same memory cells for a predetermined number of programming attempts in an effort to validly program the memory cells; the programmable non-volatile memory device further comprising: an address buffer coupled to the memory array for holding a selected address to one or more memory cells in the memory array; a data buffer coupled to the memory array for holding data to be input into the memory cells at the selected address; a controller for initiating an internal programming cycle to program the memory array in response the programming attempts made by the programming device, the internal programming cycle including accessing the memory array at the selected address held in the address buffer and writing the data held in the data buffer into the memory cells at the selected address; the controller, in the event that the data is not validly written into the addressed memory cells, repeatedly initiating the programming cycle for the same addressed memory cells in response to the continued programming attempts made by the programming device; a counter for counting a number of internal programming cycles that the controller initiates to the same address, the counter outputting a redundancy enable signal when the number of programming cycles reaches a predetermined number indicating that the addressed memory cells are defective, the predetermined number of internal programming cycles being less than or equal to the predetermined number of programming attempts; a redundancy address matching circuit operatively coupled to the counter and the address buffer for managing the replacement of defective memory cells in the memory array with the redundant memory cells, the redundancy address matching circuit assigning the redundant memory cells for the defective memory cells upon receipt of the redundancy enable signal from the counter; and the memory device subsequently routing the data to the redundant memory cells instead of the defective memory cells.

Claim 30

A method for programming a non-volatile memory device comprising the following steps: providing a memory array of addressable memory cells; providing multiple redundant memory cells for replacing defective memory cells in the memory array; addressing one or more memory cells within the memory array according to a selected address; writing data to the addressed memory cells; detecting whether the data is validly written into the addressed memory cells; in the event that the data is not validly written into the addressed memory cells, re-writing the data to the same addressed memory cells in an attempt to validly write the data into the same addressed memory cells within the memory array; counting a number of attempts to write the data to the same addressed memory cells; and replacing the addressed memory cells with the redundant memory cells when the number of write attempts reaches a predetermined number.

Claim 31

A method for programming a non-volatile memory device comprising the following steps: providing a memory array of addressable memory cells; providing multiple redundant memory cells for replacing defective memory cells in the memory array; addressing one or more memory cells within the memory array according to a selected address; writing data to the addressed memory cells; detecting whether the data is validly written into the addressed memory cells; in the event that the data is not validly written into the addressed memory cells, re-writing the data to the same addressed memory cells in an attempt to validly write the data into the same addressed memory cells within the memory array; counting a number of attempts to write the data to the same addressed memory cells; and replacing the addressed memory cells with the redundant memory cells when the number of write attempts reaches a predetermined number.

Claim 34

A method for programming a non-volatile integrated circuit memory device comprising the following steps: providing the non-volatile integrated circuit memory device having a memory array of addressable memory cells for storing electronic data, multiple redundant memory cells for replacing defective memory cells in the memory array, a data input, and an address input; supplying an address of one or more memory cells within the memory array to the address input; supplying data to the data input; commencing an attempt to program the memory device using the supplied data and address; initiating a programming cycle within the memory device in response to the program attempt by accessing the memory cells using the address at the address input and writing the data from the data input into the memory cells at the address; monitoring the memory device to determine whether the data was validly written into the memory cells; in the event the data is not validly written into the memory cells, continuing to attempt to program the memory device using the same supplied address and data for a predetermined number of programming attempts in an effort to validly program the memory device, each programming attempt causing initiation of a programming cycle within the memory device; counting the number of programming cycles made within the memory device; replacing the addressed memory cells with the redundant memory cells when the number of programming cycles reaches a predetermined number indicating that the addressed memory cells are defective; correlating within the memory device the redundant memory cells with the address of the defective memory cells at the address input; after said replacing and correlating steps, initiating a programming cycle within the memory device in response to a subsequent program attempt by writing the data from the data input into the redundant memory cells correlated to the address of the defective memory cells at the address input.

Claim 35

A method for programming a non-volatile integrated circuit memory device comprising the following steps: providing the non-volatile integrated circuit memory device having a memory array of addressable memory cells for storing electronic data, multiple redundant memory cells for replacing defective memory cells in the memory array, a data input, and an address input; supplying an address of one or more memory cells within the memory array to the address input; supplying data to the data input; commencing an attempt to program the memory device using the supplied data and address; initiating a programming cycle within the memory device in response to the program attempt by accessing the memory cells using the address at the address input and writing the data from the data input into the memory cells at the address; monitoring the memory device to determine whether the data was validly written into the memory cells; in the event the data is not validly written into the memory cells, continuing to attempt to program the memory device using the same supplied address and data for a predetermined number of programming attempts in an effort to validly program the memory device, each programming attempt causing initiation of a programming cycle within the memory device; counting the number of programming cycles made within the memory device; replacing the addressed memory cells with the redundant memory cells when the number of programming cycles reaches a predetermined number indicating that the addressed memory cells are defective; correlating within the memory device the redundant memory cells with the address of the defective memory cells at the address input; after said replacing and correlating steps, initiating a programming cycle within the memory device in response to a subsequent program attempt by writing the data from the data input into the redundant memory cells correlated to the address of the defective memory cells at the address input.