Semiconductor memory device having a serial access memory

Claim 2

A semiconductor memory device comprising: a random access memory including a plurality of memory cells and parallel read/write means for writing data and reading data into and from said memory cells on the basis of address information; and a serial access memory coupled to said random access memory, said serial access memory comprising: data register means for storing data to be written into or read from said random access memory and to be input from or output to an external signal line in serial form, said data register means including a first group of register cells and a second group of redundancy cells; first address generating means for generating a first serial access address starting from an initial address supplied from an external device; second address generating means, coupled to said first address generating means, for inputting said first serial access address and generating a second serial access address to be supplied to said data register means, said first serial access address having the same contents as said second serial access address and preceding said second serial access address by a predetermined time; redundancy decision means, coupled to said first address generating means, for determining whether said first serial access address is the same as a redundancy address; and selecting means, coupled to said redundancy decision means, for selecting one of said first and second groups of said data register means on the basis of the comparison result supplied from said redundancy decision means, said data registered in said data register means being accessed in serial form by said second serial access address, wherein when said second serial access address is supplied to said data register means, said data is input in or output from said data register means in series.

Claim 3

A semiconductor memory device as claimed in claim 1, wherein said first address generating means includes first counter means for inputting said initial access address supplied from the external device in synchronism with a first edge of a pulse signal supplied from the external device and for incrementing said first serial access address in synchronism with the subsequent first edges of said pulse signal, and said second address generating means includes second counter means for outputting said first serial access address as said second serial access address in synchronism with a second edge of said pulse signal following said first edge thereof so that said first serial access address derived from said first address generating means precedes said second serial access address derived from said second address generating means by a difference in time between the first edge and the subsequent second edge of said pulse signal.

Claim 4

A semiconductor memory device as claimed in claim 2, wherein said first serial access address precedes said second serial access address by a half of one period of said pulse signal.

Claim 5

A semiconductor memory device as claimed in claim 2, wherein said selecting means includes gate and latch means for inputting the comparison result from said redundancy decision means and outputting the same as a redundancy switching signal in synchronism with the second edge of said pulse signal.

Claim 6

A semiconductor memory device as claimed in claim 4, wherein said gate and latch means is outputting said redundancy switching signal during one period of said pulse signal from said second edge thereof.

Claim 7

A semiconductor memory device as claimed in claim 1, further comprising clock generating means for generating first and second clock pulses which are 180 degrees out of phase with each other, and said first and second address generating means generate said first and second serial access addresses in synchronism with said first and second clock pulses, respectively.

Claim 8

A semiconductor memory device as claimed in claim 6, wherein said first address generating means includes a slave flip-flop controlled by said first and second clock signals, and said second address generating means includes a master flip-flop controlled by said first and second clock signals.

Claim 9

A semiconductor memory device as claimed in claim 7, wherein said slave flip-flop provided in said first address generating means is connected to said master flip-flop provided in said second address generating means.

Claim 10

A semiconductor memory device as claimed in claim 1, wherein said first address generating means includes a plurality of slave flip-flops amounting to the number of bits forming said first serial access address, and said second address generating means includes a plurality of master flip-flops amounting to the number of bits forming said second serial access address.

Claim 11

A semiconductor memory device as claimed in claim 1, wherein said first serial access address is composed of n bits (n is an integral), and said redundancy address is composed of n bits, and wherein said redundancy decision means includes logic gate means for corresponding bits of said first serial access address and said redundancy address and for outputting the comparison result.

Claim 12

A semiconductor memory device as claimed in claim 10, wherein said logic gate means includes exclusive-NOR gates provided for the respective bits to be compared, and a NAND gate which receives output signals of said exclusive-NOR gates and outputting the comparison result.

Claim 13

A semiconductor memory device as claimed in claim 1, further comprising generating means for generating an indication signal, wherein the said first address generating means generates said first serial access address starting form said initial address when said indication signal is supplied to said first address generating means.

Claim 14

A semiconductor memory device as claimed in claim 1, wherein said initial address corresponds to a column address to be supplied to said random access memory.

Claim 15

A semiconductor memory device as claimed in claim 1, further comprising a read only memory which stores said redundancy address.

Claim 16

A semiconductor memory device as claimed in claim 1, wherein said semiconductor memory device is an image memory device which handles image data.

Claim 17

A semiconductor memory device as claimed in claim 2, wherein the first edge of said pulse signal is a falling edge and the second edge thereof is a rising edge.

Claim 18

A semiconductor memory device comprising: a random access memory including a plurality of memory cells and parallel read/write means for writing data and reading data into and from said memory cells on the basis of address information; and a serial access memory coupled to said random access memory, said address information being divided into groups each composed of a predetermined number of address bits, said serial access memory comprising: data register means for storing data to be written into or read from said random access memory and to be input from or output to an external signal line in serial form, said data register means including a first group of register cells and a second group of redundancy cells; first address generating means, provided for each of said groups of address bits, for generating a part of a first serial access address starting from an initial address for corresponding one of the groups of address bits supplied from an external device; second address generating means, provided for each of said groups of address bits and coupled to said related first address generating means, for inputting the related part of said first serial access address and generating a part of a second serial access address to be supplied to said data register means, said first serial access address having the same contents as said second serial access address and preceding said second serial access address by a predetermined time; redundancy decision means, provided for each of said groups of address bits and coupled to said first address generating means, for determining whether the part of said first serial access address is the same as a corresponding part of a redundancy address; and selecting means, coupled to said redundancy decision means, for selecting one of said first and second groups of said data register means on the basis of the comparison results supplied from said redundancy decision means provided for the groups of address bits, said data registered in said data register means being accessed in serial form by said second serial access address, wherein when said second serial access address is supplied to said data register means, said data is input in or output from said data register means in series.

Claim 19

A semiconductor memory device comprising: a random access memory including a plurality of memory cells and parallel read/write means for writing data and reading data into and from said memory cells on the basis of address information; and a serial access memory coupled to said random access memory, said address information being divided into groups each composed of a predetermined number of address bits, said serial access memory comprising: data register means for storing data to be written into or read from said random access memory and to be input from or output to an external signal line in serial form, said data register means including a first group of register cells and a second group of redundancy cells; first address generating means, provided for each of said groups of address bits, for generating a part of a first serial access address starting from an initial address for corresponding one of the groups of address bits supplied from an external device; second address generating means, provided for each of said groups of address bits and coupled to said related first address generating means, for inputting the related part of said first serial access address and generating a part of a second serial access address to be supplied to said data register means, said first serial access address having the same contents as said second serial access address and preceding said second serial access address by a predetermined time; redundancy decision means, provided for each of said groups of address bits and coupled to said first address generating means, for determining whether the part of said first serial access address is the same as a corresponding part of a redundancy address; and selecting means, coupled to said redundancy decision means, for selecting one of said first and second groups of said data register means on the basis of the comparison results supplied from said redundancy decision means provided for the groups of address bits, said data registered in said data register means being accessed in serial form by said second serial access address, wherein when said second serial access address is supplied to said data register means, said data is input in or output from said data register means in series.

Claim 20

A semiconductor memory device as claimed in claim 17, wherein said first address generating means includes first counter means for inputting said initial access address supplied from the external device in synchronism with a first edge of a pulse signal supplied from the external device and for incrementing the related part of said first serial access address in synchronism with the subsequent first edges of said pulse signal, and said second address generating means includes second counter means for outputting the related part of said first serial access address as the related part of said second serial access address in synchronism with a second edge of said pulse signal following said first edge thereof so that said first serial access address derived from said first address generating means precedes said second serial access address derived from said second address generating means by a difference in time between the first edge and the subsequent second edge of said pulse signal.

Claim 21

A semiconductor memory device as claimed in claim 18, wherein said first serial access address precedes said second serial access address by a half of one period of said pulse signal.

Claim 22

A semiconductor memory device as claimed in claim 18, wherein said selecting means includes gate and latch means for inputting the comparison results supplied from all the said redundancy decision means and generating a redundancy switching signal from the input comparison results in synchronism with the second edge of said pulse signal.