Semiconductor memory device with redundant memory cells

Claim 2

A semiconductor memory device fabricated on a semiconductor chip, comprising: (a) a purality of memory cells arranged in rows and columns, said memory cells in the respective rows being coupled to a plurality of word lines, respectively, each of said memory cells having a possibility of a defective memory cell; (b) a plurality of redundant memory cells arranged in rows, said redundant memory cells in the respective rows being coupled to a plurality of redundant word lines, respectively; (c) address means for receiving address signals including a row address signal representative of a row address; (d) redundant decoder means having a plurality of redundant decoder units equal in number to the rows of said redundant memory cells, each of said redundant decoder units being capable of memorizing a row address assigned to said defective memory cell, each of said redundant decoder units being operative to produce a replacing signal for activating one of said redundant word lines when the row address memorized therein is identical with the row address represented by said row address signal; (e) address decoding means having a row address decoder circuit, said row address decoder circuit being operative to activaate one of said word lines corresponding to the row address represented by said row address signal in the absence of said replacing signal, said row address decoder circuit being shifted into an inactive state in the presence of said replacing signal; and (f) redundant state detection means having an address detecting section operative to produce a first detecting signal when the row address represented by said row address signal is identical with the row address memorized in one of said redundant decoder units, wherein said address detecting section comprises a single bypassing transistor coupled between a first node applied with a first voltage level and a second node, a single bootstrapping circuit operative to supply a gate electrode of said bypassing transistor with a second voltage level higher than said first voltage level by a value larger than a threshold voltage of said bypassing transistor, and a plurality of activaating transistors coupled in parallel between a source of a third voltage level and said bootstrapping circuit and having respective gate electrodes respectively supplied with replacing signals produced by said redundant decoder units, respectively, said second node being supplied with a voltage level lower than said first voltage level.

Claim 3

A semiconductor memory device as set forth in claim 1, in which said bootstrapping circuit comprises a capacitor coupled between said activating transistors and said bypassing transistor, and a field effect transistor coupled between the gate electrode of said bypassing transistor and said second node.

Claim 4

A semiconductor memory device as set forth in claim 2, in which said address detecting section further comprises a resetting transistor coupled between said bootstrapping circuit and a source of a fourth voltage level.

Claim 5

A semiconductor memory device as set forth in claim 2, in which said redundant state detection means further have a replacement memorizing section capable of producing a second detecting signal when said defective memory cell was replaced with said redundant memory cell.

Claim 6

A semiconductor memory device as set forth in claim 4, in which said replacement memorizing section has a series combination of resistor elements coupled between a testing node and said first node, and a fuse element coupled between said first node and said second node.

Claim 7

A semiconductor memory device as set forth in claim 5, in which each of said resistor elements is formed by a field effect transistor having a gate electrode coupled to a source electrode thereof.

Claim 8

A semiconductor memory device as set forh in claim 6, in which said bypassing transistor, said field effect transistor forming part of said bootstrapping circuit, said activating transistors and field effect transistors forming part of said replacement memorizing section are formed by n-channel type field effect transistors, respectively.

Claim 9

A semiconductor memory device as set forth in claim 7, in which said first voltage level and said third voltage level are approximately equal to each other and in which said fourth voltage level is approximately equal to the ground voltage level.

Claim 10

A semiconductor memory device as set forth in claim 8, in which each of said redundanat decoder units has a redundant decoder circuit operaative to memorize the row address assigned to said defective memory cell and operaative to produce a high voltage signal when the row address memorized therein is identical with the row address represented by said row address signal, and an n-channel type field effect transistor having a gate electrode applied with the high voltage signal and coupled between the source of said fourth voltage level and a node where said row decoder circuit, one of said redundant word lines and said activating transistor are electrically connected.

Claim 11

A semiconductor memory device fabricated on a semiconductor chip, comprising: (a) a plurality of memory cells arranged in rows and coluns, said memory cells in the respective rows being coupled to a plurality of word lines, respectively, each of said memory cells having a possibility of a defective memory cell; (b) a plurality of redundant memory cells arranged in rows, said redundant memory cells in the respective rows being coupled to a plurality of redundant word lines, respectively; (c) address means for receiving address signals including a row address signal representative of a row address; (d) redundant decoder means having a plurality of redundant decoder units equal in number to the rows of said redundant memory cells, each of said redundant decoder units being capable of memorizing a row address assigned to said defective memory cell, each of said redundant decoder units being operative to produce a replacing signal for activating one of said redundant word lines when the row address memorized therein is identical with the row address represented by said row address signal; (e) address decoding means having a row address decoder circuit, said row address decoder circuit being operative to activate one of said word lines corresponding to the row address represented by said row address signal in the absence of said replacing signal, said row address decoder circuit being shifted into an inactive state in the presence of said replaciing signal; and (f) redundant state detection means having an address detecting section operative to produce a first detecting signal when the row address represented by said row address signal is identicla with the row address memorized in one of said redundant decoder units, and a replacement memorizing section capable of producing a second detecting signal when said defective memory cell was replaced with said redundant memory cell, in which said address detecting section comprises an n-channel type single bypassing transistor coupled between a first node applied with a first voltage level and a second node where said first and second detecting signals appear in the form of currents, a single bootstrappping circuit operative to supply a gate electrode of saidi bypassing transistor with a second voltage level higher than said first voltage level by a value larger than a threshold voltage of said bypassing transistor, and a plurality of activating transistors coupled in parallel between a source of a third voltage level and said bootstrapping circuit and having respective gate electrodes respectively supplied with the replacing signals produced by said redundant decoder units, respectively, said bootstrapping circuit having a capacitor coupled between said activating transistors and the gate electrode of said bypassing transistor and an n-channel type field effect transistor coupled between the gate of said bypassing transistor and said second node, said second node being supplied with a voltage level slightly lower than said first voltage level, and in which said replacement memorizing secion has a series combination of n-channel type field effect transistors coupled between a testing node and said first node, and a fuse element coupled between said first node and said second node, each of said n-channel type field effect transistors of said series combination having a gate electrode coupled to a source electrode thereof.

Claim 12

A semiconductor memory device fabricated on a semiconductor chip, comprising: (a) a plurality of memory cells arranged in rows and coluns, said memory cells in the respective rows being coupled to a plurality of word lines, respectively, each of said memory cells having a possibility of a defective memory cell; (b) a plurality of redundant memory cells arranged in rows, said redundant memory cells in the respective rows being coupled to a plurality of redundant word lines, respectively; (c) address means for receiving address signals including a row address signal representative of a row address; (d) redundant decoder means having a plurality of redundant decoder units equal in number to the rows of said redundant memory cells, each of said redundant decoder units being capable of memorizing a row address assigned to said defective memory cell, each of said redundant decoder units being operative to produce a replacing signal for activating one of said redundant word lines when the row address memorized therein is identical with the row address represented by said row address signal; (e) address decoding means having a row address decoder circuit, said row address decoder circuit being operative to activate one of said word lines corresponding to the row address represented by said row address signal in the absence of said replacing signal, said row address decoder circuit being shifted into an inactive state in the presence of said replaciing signal; and (f) redundant state detection means having an address detecting section operative to produce a first detecting signal when the row address represented by said row address signal is identicla with the row address memorized in one of said redundant decoder units, and a replacement memorizing section capable of producing a second detecting signal when said defective memory cell was replaced with said redundant memory cell, in which said address detecting section comprises an n-channel type single bypassing transistor coupled between a first node applied with a first voltage level and a second node where said first and second detecting signals appear in the form of currents, a single bootstrappping circuit operative to supply a gate electrode of saidi bypassing transistor with a second voltage level higher than said first voltage level by a value larger than a threshold voltage of said bypassing transistor, and a plurality of activating transistors coupled in parallel between a source of a third voltage level and said bootstrapping circuit and having respective gate electrodes respectively supplied with the replacing signals produced by said redundant decoder units, respectively, said bootstrapping circuit having a capacitor coupled between said activating transistors and the gate electrode of said bypassing transistor and an n-channel type field effect transistor coupled between the gate of said bypassing transistor and said second node, said second node being supplied with a voltage level slightly lower than said first voltage level, and in which said replacement memorizing secion has a series combination of n-channel type field effect transistors coupled between a testing node and said first node, and a fuse element coupled between said first node and said second node, each of said n-channel type field effect transistors of said series combination having a gate electrode coupled to a source electrode thereof.