US5331196A
Expired / Lapsed
US
⏱️ 0.0 years remaining
One-time, voltage-programmable, logic element
Assignee: Round Rock Research LLC
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Filing: 1993-08-31
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Granted: 1994-07-19
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Expires: 2013-08-31
Abstract
Abstract A one-time, voltage-programmable, logic element has an antifuse element constructed within a trench etched in a silicon substrate. A sidewall of the trench abuts a diffusion region. The trench is lined with a nitride dielectric layer, which is in turn covered by polycrystalline silicon. The polycrystalline silicon serves as a voltage reference line. In a preferred embodiment, the diffusion region forms a first source/drain region of a field-effect transistor. In order to program the element, a voltage sufficient to rupture the nitride dielectric layer is applied between the diffusion region and the reference line. The transistor is utilized to isolate a particular logic element from other logic elements.
Inventors
- 👤 Tyler A. Lowrey
- 👤 Ruojia Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:29
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/16; H; H10; H10B; H10B20/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
87 words
A one-time, voltage-programmable logic element comprising: an insulated-gate, field-effect transistor, said transistor having a channel region within a semiconductor substrate, and first and second source/drain regions interconnected by said channel region, said first source/drain region being coupled to an output line; a trench within said substrate abutting said second source/drain region; a dielectric layer which lines said trench; a conductive plug within said trench, said dielectric layer being disposed between said plug and said second source/drain region, and said conductive plug being coupled to a reference voltage,
Claim 2
Dependent Claim
87 words
A one-time, voltage-programmable logic element comprising: an insulated-gate, field-effect transistor, said transistor having a channel region within a semiconductor substrate, and first and second source/drain regions interconnected by said channel region, said first source/drain region being coupled to an output line; a trench within said substrate abutting said second source/drain region; a dielectric layer which lines said trench; a conductive plug within said trench, said dielectric layer being disposed between said plug and said second source/drain region, and said conductive plug being coupled to a reference voltage,
Claim 3
Dependent Claim
36 words
The one-time, voltage-programmable logic element of claim 1, wherein the dielectric layer functions as an antifuse link which, when subjected to high voltage programming, ruptures and permanently couples said conductive plug to said second source/drain region.
Claim 4
Dependent Claim
15 words
The one-time, voltage-programmable logic element of claim 2, wherein said dielectric layer comprises silicon nitride.
Claim 5
Dependent Claim
150 words
A pair of one-time voltage-programmable logic elements comprising: a pair of spaced-apart insulated-gate, field-effect transistors, each of said transistors having a gate which overlies and defines a channel region within a semiconductor substrate, said gate being dielectrically insulated from said substrate, each of said transistors also having first and second source/drain regions interconnected by that transistor's channel region, said first source/drain region of each transistor being coupled to an output line; a trench extending downwardly into the substrate between said pair of transistors, said trench abutting said first source/drain region of each transistor; a dielectric layer which lines said trench; and a conductive plug which fills said trench and extends upwardly from the substrate, said plug being dielectrically insulated from the gate of each transistor, said dielectric layer being disposed between said plug and said second source/drain region of each transistor, said conductive plug being coupled to a reference voltage.
Claim 6
Dependent Claim
150 words
A pair of one-time voltage-programmable logic elements comprising: a pair of spaced-apart insulated-gate, field-effect transistors, each of said transistors having a gate which overlies and defines a channel region within a semiconductor substrate, said gate being dielectrically insulated from said substrate, each of said transistors also having first and second source/drain regions interconnected by that transistor's channel region, said first source/drain region of each transistor being coupled to an output line; a trench extending downwardly into the substrate between said pair of transistors, said trench abutting said first source/drain region of each transistor; a dielectric layer which lines said trench; and a conductive plug which fills said trench and extends upwardly from the substrate, said plug being dielectrically insulated from the gate of each transistor, said dielectric layer being disposed between said plug and said second source/drain region of each transistor, said conductive plug being coupled to a reference voltage.
Claim 7
Dependent Claim
17 words
The pair of one-time voltage-programmable logic elements of claim 4, wherein said dielectric layer comprises silicon nitride.
Claim 8
Dependent Claim
88 words
The pair of one-time, voltage-programmable logic elements of claim 5, wherein the dielectric layer forms an antifuse link for each transistor, either of which may be selectively ruptured so as to couple said conductive plug to the second source/drain region of either transistor by applying a programming voltage between the conductive plug and the first source/drain region, and activating the gate of the transistor associated with the link to be programmed so that a voltage is seen across the link to be programmed that exceeds its breakdown voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-18 | 1998-01-17 | 1998-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-18 | 2002-01-17 | 2002-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-18 | 2006-01-17 | 2006-07-19 | $7700.00 | Window Closed / Lapsed |