Anti-fuse ROM programming circuit

Claim 2

An on-chip programming circuit for programming anti-fuse elements of an integrated-circuit ROM, comprising: a series pass transistor for directing a high voltage programming voltage to a high-voltage programming line for anti-fuse elements; means for providing a fixed voltage to the gate terminal of the series pass transistor, wherein the fixed voltage is insufficient to turn on the series pass transistor; means for directly superimposing an alternating voltage directly onto the gate terminal of the series pass transistor wherein the peaks of the alternating voltage superimposed on the gate terminal of the series pass transistor turn on the series pass transistor to apply the programming voltage to the main high voltage programming line of an anti-fuse memory array; wherein the means for directly superimposing an alternating voltage directly onto the gate terminal of the series pass transistor includes a capacitor having one terminal connected to the gate terminal of the series pass transistor and having another terminal connected to an alternating voltage source.

Claim 3

The on-chip programming circuit of claim 1 wherein the means for providing a fixed voltage to the gate terminal of the series pass transistor includes a saturating transistor having a drain terminal connected to the high voltage programming voltage, having a source terminal connected to the gate terminal of the series pass transistor, and having a gate terminal connected to a voltage sufficient to saturate the saturating transistor.

Claim 4

The on-chip programming circuit of claim 1 including means for shorting the gate terminal of the series pass transistor to a ground voltage.

Claim 5

The on-chip programming circuit of claim 1 including means for shorting the source terminal of the series pass transistor to a ground voltage.

Claim 6

An on-chip programming circuit for programming anti-fuse elements of an integrated-circuit ROM, comprising: an input terminal for the programming circuit at which is provided a programming voltage; an output terminal of the programming circuit; a first series transistor having a drain terminal connected to the input terminal of the programming circuit and having a source terminal connected to the output terminal of the programming circuit; a saturated transistor having a drain terminal connected to the input terminal of the programming circuit, having a source terminal connected to the gate terminal of the first series transistor, and having a gate terminal to which is applied a positive voltage source so that the second saturated transistor remains in the saturated mode of operation; an oscillator input terminal; a series capacitor having a first terminal connected to the oscillator input terminal and a second terminal connected to the gate terminal of the series transistor; an oscillator circuit connected to the oscillator input terminal and providing an alternating voltage signal through the series capacitor directly to the gate terminal of the first series transistor, where the oscillator provides a peak voltage sufficient to turn on the first series transistor so that the programming voltage is applied to the output terminal of the circuit voltage during the positive peaks of the oscillator voltage.

Claim 7

An on-chip programming circuit for programming anti-fuse elements of an integrated-circuit ROM, comprising: an input terminal for the programming circuit at which is provided a programming voltage; an output terminal of the programming circuit; a first series transistor having a drain terminal connected to the input terminal of the programming circuit and having a source terminal connected to the output terminal of the programming circuit; a saturated transistor having a drain terminal connected to the input terminal of the programming circuit, having a source terminal connected to the gate terminal of the first series transistor, and having a gate terminal to which is applied a positive voltage source so that the second saturated transistor remains in the saturated mode of operation; an oscillator input terminal; a series capacitor having a first terminal connected to the oscillator input terminal and a second terminal connected to the gate terminal of the series transistor; an oscillator circuit connected to the oscillator input terminal and providing an alternating voltage signal through the series capacitor directly to the gate terminal of the first series transistor, where the oscillator provides a peak voltage sufficient to turn on the first series transistor so that the programming voltage is applied to the output terminal of the circuit voltage during the positive peaks of the oscillator voltage.

Claim 8

The programming circuit of claim 5 wherein the programming voltage is 13 volts.

Claim 9

The programming circuit of claim 6 wherein the output alternating voltage of the oscillator circuit is 6 volts peak.

Claim 10

The programming circuit of claim 5 including a first shunt transistor having a source terminal, a drain terminal, and a gate terminal, wherein the drain terminal is connected to the output terminal of the circuit, wherein the source terminal is connected to a ground potential; and wherein the gate terminal is connected to a first logic signal which goes HIGH to turn on the first shunt transistor and shunt the output terminal of the circuit to the ground potential.

Claim 11

The programming circuit of claim 5 including a second shunt transistor having a source terminal, a drain terminal, and a gate terminal, wherein the drain terminal is connected to the gate terminal of the first series transistor, wherein the gate terminal is connected to a positive voltage; and wherein the source terminal is connected to a logic terminal which has a signal logic signal applied thereto for disabling the first series transistor.

Claim 12

The programming circuit of claim 5 including selection means for connecting an anti-fuse element to be programmed to the output terminal of the programming circuit to provide the programming voltage to the anti-fuse element.

Claim 13

The programming circuit of claim 5 including means for activating the programming circuit by applying a positive voltage signal to the gate terminal of the saturated transistor.

Claim 14

The programming circuit of claim 11 wherein the means for activating the programming circuit by applying a positive voltage signal to the gate terminal of the second saturated transistor includes means for starting the oscillator circuit.

Claim 15

The programming circuit of claim 5 including a column select transistor having a drain terminal connected to the output terminal of the programming circuit, having a source terminal connected to an anti-fuse link, and a gate terminal connected to a 15 volt high voltage column address voltage to provide a 13 volt programming voltage to the anti-fuse link through the column select transistor.

Claim 18

The method of claim 9 including the step of gating the programming voltage to the anti-fuse device through a switching transistor.