Semiconductor device

Claim 2

A semiconductor device which comprises: first and second power terminals; memory means having an impedance capable of being set at one of two levels in a nonvolatile state; MOSFET switching means connected in series with said memory means between said first and second power supply terminals, said switching means including a gate; and control means connected between said gate of said MOSFET switching means and the junction of said memory means and said MOSFET switching means for controlling the conduction of said switching means according to the voltage at the junction between said memory means and said switching means, said control means including an odd number of series-connected inverters and a capacitor connected between one of said power terminals and an output terminal of one of said inverters.

Claim 3

A semiconductor device which comprises: first and second power supply terminals memory means having an impedance capable of being set at one of two levels in a nonvolatile state; switching means connected in series with said memory means between said first and second power supply terminals, said switching means including a control terminal for receiving signals that control the conductivity of said switching means; a first input terminal coupled to the junction between said memory means and said switching means; pulse generator means coupled to said switching means for generating a pulse from an output terminal to said control terminal of said switching means; a second input terminal connected to said output terminal of said pulse generator means; and latch means, coupled to said memory means, said switching means and said pulse generator means, for latching the voltage level at said first input terminal upon receipt at said second input terminal of said pulse from said pulse generator means, said latch means including a flip-flop circuit comprising a pair of NOR gates, and a MOSFET connected between one of said power supply terminals and said first input terminal and having a gate coupled to said flip-flop circuit.

Claim 4

A semiconductor device which comprises: first and second power supply terminals memory means having an impedance capable of being set at one of two levels in a nonvolatile state; switching means connected in series with said memory means between said first and second power supply terminals, said switching means including a control terminal for receiving signals that control the conductivity of said switching means; a first input terminal coupled to the junction between said memory means and said switching means; pulse generator means coupled to said switching means for generating a pulse from an output terminal to said control terminal of said switching means; a second input terminal connected to said output terminal of said pulse generator means; and latch means, coupled to said memory means, said switching means and said pulse generator means, for latching the voltage level at said first input terminal upon receipt at said second input terminal of said pulse from said pulse generator means, said latch means including a flip-flop circuit comprising a pair of NOR gates, and a MOSFET connected between one of said power supply terminals and said first input terminal and having a gate coupled to said flip-flop circuit.

Claim 5

A semiconductor device comprising: first and second power supply terminals; memory means having an impedance capable of being set at one of two levels in a nonvolatile state; switching means connected in series with said memory means between said first and second power supply terminals, said switching means including a control terminal for receiving signals that control the conductivity of said switching means; pulse generator means coupled to said switching means for generating a pulse from an output terminal to said switching means control terminal; and latch means, coupled to said memory means, said switching means and said pulse generator means for latching the voltage level at the junction of said memory means and said switching means, said latch means including an even number of inverters connected in series to an output terminal of said latch means, a first MOSFET having a gate and whose conduction path is connected between said inverters and said junction between said memory means and said switching means, and a second MOSFET having a gate and being connected in parallel with said even number of inverters, and wherein said pulse generator means output is coupled to the gate of the first MOSFET and is also coupled through an output inverter to the gate of the second MOSFET.

Claim 6

A semiconductor device comprising: first and second power supply terminals; memory means having an impedance capable of being set at one of two levels in a nonvolatile state; switching means connected in series with said memory means between said first and second power supply terminals, said switching means including a control terminal for receiving signals that control the conductivity of said switching means; pulse generator means coupled to said switching means for generating a pulse from an output terminal to said switching means control terminal; and latch means, coupled to said memory means, said switching means and said pulse generator means for latching the voltage level at the junction of said memory means and said switching means, said latch means including an even number of inverters connected in series to an output terminal of said latch means, a first MOSFET having a gate and whose conduction path is connected between said inverters and said junction between said memory means and said switching means, and a second MOSFET having a gate and being connected in parallel with said even number of inverters, and wherein said pulse generator means output is coupled to the gate of the first MOSFET and is also coupled through an output inverter to the gate of the second MOSFET.

Claim 7

An semiconductor device which comprises: flip-flop circuit means having first and second output terminals; memory means having an impedance which is capable of being set at one of two levels in a nonvolatile state; first capacitance means coupled to the first output terminal of said flip-flop circuit means and to said memory means; and second capacitance means connected to the second output terminal of said flip-flop circuit means and having a different capacitance value from that of said first capacitance means.

Claim 8

An semiconductor device which comprises: flip-flop circuit means having first and second output terminals; memory means having an impedance which is capable of being set at one of two levels in a nonvolatile state; first capacitance means coupled to the first output terminal of said flip-flop circuit means and to said memory means; and second capacitance means connected to the second output terminal of said flip-flop circuit means and having a different capacitance value from that of said first capacitance means.

Claim 9

A semiconductor device according to claim 4, wherein said flip-flop circuit means comprises CMOS elements.

Claim 10

A semiconductor device according to claim 4, wherein said memory means includes a polysilicon fuse capable of being blown by laser beams.

Claim 11

A semiconductor device according to claim 4, wherein said memory means is formed of a polysilicon resistor whose resistivity is capable of being reduced by laser annealing.

Claim 12

A semiconductor device according to claim 4, wherein said second capacitance means is connected to the second output terminal of the flip-flop circuit through said memory means.

Claim 13

A semiconductor memory device responsive to an address signal which comprises: normal memory cells; spare memory cells; normal decoder means coupled to said normal memory cells for selecting one of said normal memory cells according to said address signal; spare decoder means coupled to said spare memory cells and said normal decoder means for selecting one of said spare memory cells and for inhibiting said normal decoder means; and programming means coupled to said spare decoder means for programming the selection of said spare decoder means, said programming means including first and second power supply terminals, memory means having an impedance capable of being set at one of two levels in a nonvolatile state, switching means connected to said memory means in series between said first and second power supply terminals, control means coupled to the junction of said memory means and said switching means and to an input of said switching means for controlling the conduction of said switching means according to the voltage of the junction between said memory means and said switching means, said control means including delay means between said junction and said switching means input, and selector means coupled to said control means and said spare decoder means for supplying a signal to said spare decoder means according to the voltage at the junction between said memory means and said switching means.

Claim 14

A semiconductor memory device responsive to an address signal which comprises: normal memory cells; spare memory cells; normal decoder means coupled to said normal memory cells for selecting one of said normal memory cells according to said address signal; spare decoder means coupled to said spare memory cells and said normal decoder means for selecting one of said spare memory cells and for inhibiting said normal decoder means; and programming means coupled to said spare decoder means for programming the selection of said spare decoder means, said programming means including first and second power supply terminals, memory means having an impedance capable of being set at one of two levels in a nonvolatile state, switching means connected to said memory means in series between said first and second power supply terminals, control means coupled to the junction of said memory means and said switching means and to an input of said switching means for controlling the conduction of said switching means according to the voltage of the junction between said memory means and said switching means, said control means including delay means between said junction and said switching means input, and selector means coupled to said control means and said spare decoder means for supplying a signal to said spare decoder means according to the voltage at the junction between said memory means and said switching means.

Claim 15

A semiconductor memory device according to claim 9, wherein said switching means comprises an N channel MOSFET having a gate and connected to said memory means and wherein said control means includes an odd number of series-connected inverters coupled to the junction between said memory means and said MOSFET for supplying an inverted signal to the gate of the N channel MOSFET, and a capacitor connected between one of said supply terminals and an output terminal of one of said odd number of inverters.

Claim 16

A semiconductor memory device according to claim 9, wherein said memory means comprises a polysilicon fuse connected to said switching means and a switch connected between the junction of said polysilicon fuse and said switching means and said second power supply terminal such that said polysilicon fuse is blown when the switch is rendered conductive.

Claim 17

A semiconductor memory device responsive to an address signal which comprises: normal memory cells; spare memory cells; normal decoder means coupled to said normal memory cells for selecting one of said normal memory cells according to said address signals; spare decoder means coupled to said spare memory cells and said normal decoder means for selecting one of said spare memory cells and for inhibiting said normal decoder means; and programming means coupled to said spare decoder means for programming the selection of said spare decoder means, said programming means including first and second power supply terminals, memory means having an impedance capable of being set at one of two levels in a nonvolatile state, switching means connected to said memory means in series between said first and second power supply terminals and having a control terminal for receiving signals that control the conductivity of said switching means, pulse generator means for generating a pulse at an output terminal of said pulse generating means to said control terminal of said switching means, and latch means for latching the voltage level at the junction between said memory means and said switching means upon receipt of said pulse from said pulse generator means.

Claim 18

A semiconductor memory device responsive to an address signal which comprises: normal memory cells; spare memory cells; normal decoder means coupled to said normal memory cells for selecting one of said normal memory cells according to said address signals; spare decoder means coupled to said spare memory cells and said normal decoder means for selecting one of said spare memory cells and for inhibiting said normal decoder means; and programming means coupled to said spare decoder means for programming the selection of said spare decoder means, said programming means including first and second power supply terminals, memory means having an impedance capable of being set at one of two levels in a nonvolatile state, switching means connected to said memory means in series between said first and second power supply terminals and having a control terminal for receiving signals that control the conductivity of said switching means, pulse generator means for generating a pulse at an output terminal of said pulse generating means to said control terminal of said switching means, and latch means for latching the voltage level at the junction between said memory means and said switching means upon receipt of said pulse from said pulse generator means.

Claim 19

A semiconductor memory device according to claim 12, wherein said latch means comprises a flip-flop circuit including a pair of NOR gates, a first input terminal connected to the junction between said memory means and said switching means, a second input terminal connected to the output terminal of said pulse generator means, and a MOSFET connected between one of said power supply terminals and the first input terminal and having a gate coupled to said flip-flop circuit.

Claim 20

A semiconductor memory device according to claim 12, wherein said latch means comprises an even number of inverters connected in series to an output terminal of said latch means, a first MOSFET having a gate and a conduction path connected between said inverters and the junction between said memory means and said switching means, and a second MOSFET having a gate and being coupled to said even number of inverters, and wherein said output terminal of said pulse generator means is coupled to the gate of the first MOSFET and is also coupled through an output inverter to the gate of the second MOSFET.

Claim 21

A semiconductor memory device according to claim 12, wherein said memory means comprises a polysilicon fuse connected to said switching means and a switch connected between the junction of said polysilicon fuse and said switching means and the second power supply terminal such that said polysilicon fuse is blown when the switch is rendered conductive.

Claim 22

A semiconductor memory device responsive to an address signal which comprises: normal memory cells; spare memory cells; normal decoder means coupled to said normal memory cells for selecting one of said normal memory cells according to said address signal; spare decoder means coupled to said normal decoder means and to said spare memory cells for selecting one of said spare memory cells and for inhibiting said normal decoder means; memory means having an impedance capable of being set at one of two levels in a nonvolatile state; and programming means coupled to said memory means and said spare decoder means for programming the selection of said spare decoder means, said programming means including flip-flop circuit means having first and second output terminals, first capacitance means connected to the first output terminal of said flip-flop circuit means said coupled to said memory means, and second capacitance means connected to the second output terminal of said flip-flop circuit means and having a different capacitance value from that of the first capacitance means.

Claim 23

A semiconductor memory device responsive to an address signal which comprises: normal memory cells; spare memory cells; normal decoder means coupled to said normal memory cells for selecting one of said normal memory cells according to said address signal; spare decoder means coupled to said normal decoder means and to said spare memory cells for selecting one of said spare memory cells and for inhibiting said normal decoder means; memory means having an impedance capable of being set at one of two levels in a nonvolatile state; and programming means coupled to said memory means and said spare decoder means for programming the selection of said spare decoder means, said programming means including flip-flop circuit means having first and second output terminals, first capacitance means connected to the first output terminal of said flip-flop circuit means said coupled to said memory means, and second capacitance means connected to the second output terminal of said flip-flop circuit means and having a different capacitance value from that of the first capacitance means.

Claim 24

A semiconductor memory device according to claim 16, wherein said flip-flop circuit means includes CMOS circuits.

Claim 25

A semiconductor memory device according to claim 16, wherein said memory means includes a polysilicon fuse capable of being blown by laser beams.

Claim 26

A semiconductor memory device according to claim 16, wherein said memory means includes a polysilicon resistor whose resistivity capable of being reduced by laser annealing.

Claim 27

A semiconductor memory device according to claim 16, wherein said second capacitance means is connected to the second output terminal of the flip-flop circuit means and to said memory means.

Claim 28

A semiconductor memory device responsive to an address signal and an inverted address signal which comprises: normal memory cells; spare memory cells; normal decoder means coupled to said normal memory cells for selecting one of said normal memory cells according to said address signal; spare decoder means coupled to said spare memory cells and said normal decoder means for selecting one of said spare memory cells and for inhibiting said normal decoder means; and programming means coupled to said spare decoder means for programming the selection of said spare decoder means, said programming means including a first power supply terminal, an output terminal, a plurality of first circuits each comprising a first fuse connected to a MOSFET having a first channel and a gate receiving at least a portion of said address signal, a plurality of second circuits each comprising a second fuse connected to a MOSFET having said first channel and a gate receiving at least a portion of said inverter address signal, said plurality of first and second circuits being connected in parallel between said first power supply terminal and said output terminal, a plurality of third circuits each comprising a third fuse connected to a MOSFET having a second channel and a gate receiving at least a portion of said address signal, and a plurality of fourth circuits each comprising a fourth fuse connected to a MOSFET having said second channel and a gate receiving at least a portion of said inverted address signal, each said third circuit being connected in parallel and in parallel with each said fourth circuit, one of said first and third fuses and one of said second and fourth fuses being blown in accordance with a signal representing a defective normal memory cell.

Claim 29

A semiconductor memory device responsive to an address signal and an inverted address signal which comprises: normal memory cells; spare memory cells; normal decoder means coupled to said normal memory cells for selecting one of said normal memory cells according to said address signal; spare decoder means coupled to said spare memory cells and said normal decoder means for selecting one of said spare memory cells and for inhibiting said normal decoder means; and programming means coupled to said spare decoder means for programming the selection of said spare decoder means, said programming means including a first power supply terminal, an output terminal, a plurality of first circuits each comprising a first fuse connected to a MOSFET having a first channel and a gate receiving at least a portion of said address signal, a plurality of second circuits each comprising a second fuse connected to a MOSFET having said first channel and a gate receiving at least a portion of said inverter address signal, said plurality of first and second circuits being connected in parallel between said first power supply terminal and said output terminal, a plurality of third circuits each comprising a third fuse connected to a MOSFET having a second channel and a gate receiving at least a portion of said address signal, and a plurality of fourth circuits each comprising a fourth fuse connected to a MOSFET having said second channel and a gate receiving at least a portion of said inverted address signal, each said third circuit being connected in parallel and in parallel with each said fourth circuit, one of said first and third fuses and one of said second and fourth fuses being blown in accordance with a signal representing a defective normal memory cell.