US4380804A
Expired / Lapsed
US
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Earom cell matrix and logic arrays with common memory gate
Assignee: MagnaChip Semiconductor Ltd
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Filing: 1980-12-29
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Granted: 1983-04-19
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Expires: 2000-12-29
Abstract
Abstract A three gate programmable memory cell comprised of a variable threshold memory element medial of two access gate elements, together forming a series path whose conductive state can be altered by any one of the series elements. Each cell has lines for individually accessing the three gate electrodes, in addition to line connections to opposite ends of the conductive path formed by the elements in series. In one form, an alterable threshold transistor is connected in series between two field effect transistors, one of the two controlling cell addressing and the other actuating the read mode. The cell is erased with a high voltage pulse on the memory line. Subsequent programming of the cell is defined by the voltage states on the word and bit lines of the addressing transistor in time coincidence with an opposite polarity, shorter duration pulse on the memory line. The logic state stored in the cell is defined by the presence or absence of a conductive path through the cell when all three gates are biased to their read mode levels. A unitary configuration of the cell includes a single substrate, with a channel defined between doped node regions. Electrically isolated gate electrodes of the three transistors are symmetrically disposed adjacent each other over the channel to control its conductivity in segments. The cells are amenable to being grouped in arrays, while retaining the independence of the high voltage memory line and the flexibility of individual row and column addresses.
Inventors
- 👤 George C. Lockwood
- 👤 Murray L. Trudel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 01:43
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/04; G11C16/12; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17712; H10; H10D; H10D30/00; H10D30/60; H10D30/69
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
417 words
A three element programmable memory cell capable of being erased, programmed and read using a first address line, a second address line, a memory line, a read line and a third line, comprising: a first field effect transistor, having a gate electrode, electrically coupled to said first address line, a first conductive path electrode, electrically coupled to said second address line, and a first conductive path virtual node; a second field effect transistor, having a gate electrode, electrically coupled to said read line, a first conductive path electrode, electrically coupled to said third line, and a first conductive path virtual node; memory means, having a gate electrode, electrically coupled to said memory line, first and second conductive path virtual nodes respectively coupled to said first conductive path virtual nodes of said first and second field effect transistors, and a threshold voltage level responsive to a voltage pulse on said memory line in time coincidence with the formation of a conductive path through said first field effect transistor between said second address line and said first conductive path virtual node, for forming a conductive path between said first and second conductive path virtual nodes of said memory means in response to the relative mangitude between a voltage on said memory line and an alterable threshold voltage in said memory means; means for generating voltages, coupled to the lines of said memory means, said first field effect transistor and said second field effect transistor, characterized in its provision of voltage sequences, including; a first sequence, suitable to program said cell to a first binary state, comprising, a coupling of voltages to said first address line and said memory line in substantial time synchronism with substantially zero voltages on said second address line and on said read line; a second sequence, suitable to program said cell to an alternate, second binary state, comprising, a coupling of voltages to said memory line and to said first and second address electrodes, suitable to electrically decouple said second address line from said first conductive path virtual node of said first field effect transistor, in substantial time synchronism with a substantially zero voltage on said read line; and a third sequence, suitable to read the binary state programmed into said cell, comprising, a coupling of voltages to said first address line and to said read line in substantial time synchronism with a substantially zero voltage on said memory line; and means for sensing the conductivity between said second address line and said third line.
Claim 2
Dependent Claim
417 words
A three element programmable memory cell capable of being erased, programmed and read using a first address line, a second address line, a memory line, a read line and a third line, comprising: a first field effect transistor, having a gate electrode, electrically coupled to said first address line, a first conductive path electrode, electrically coupled to said second address line, and a first conductive path virtual node; a second field effect transistor, having a gate electrode, electrically coupled to said read line, a first conductive path electrode, electrically coupled to said third line, and a first conductive path virtual node; memory means, having a gate electrode, electrically coupled to said memory line, first and second conductive path virtual nodes respectively coupled to said first conductive path virtual nodes of said first and second field effect transistors, and a threshold voltage level responsive to a voltage pulse on said memory line in time coincidence with the formation of a conductive path through said first field effect transistor between said second address line and said first conductive path virtual node, for forming a conductive path between said first and second conductive path virtual nodes of said memory means in response to the relative mangitude between a voltage on said memory line and an alterable threshold voltage in said memory means; means for generating voltages, coupled to the lines of said memory means, said first field effect transistor and said second field effect transistor, characterized in its provision of voltage sequences, including; a first sequence, suitable to program said cell to a first binary state, comprising, a coupling of voltages to said first address line and said memory line in substantial time synchronism with substantially zero voltages on said second address line and on said read line; a second sequence, suitable to program said cell to an alternate, second binary state, comprising, a coupling of voltages to said memory line and to said first and second address electrodes, suitable to electrically decouple said second address line from said first conductive path virtual node of said first field effect transistor, in substantial time synchronism with a substantially zero voltage on said read line; and a third sequence, suitable to read the binary state programmed into said cell, comprising, a coupling of voltages to said first address line and to said read line in substantial time synchronism with a substantially zero voltage on said memory line; and means for sensing the conductivity between said second address line and said third line.
Claim 3
Dependent Claim
116 words
The cell recited in claim 1, wherein said cell is unitary in structure, having a substrate with first and second conductive regions, electrically common with said first conductive path electrodes in said first and second field effect transistors, respectively, joined by a current flow channel in said substrate, a first transistor gate electrode electrically insulated from said substrate and in proximity to said channel adjacent said first conductive region, a second transistor gate electrode electrically insulated from said substrate and in proximity to said channel adjacent said second conductive region, and a memory means gate electrode electrically insulated from said substrate and in proximity to said channel medial of said first and second transistor gate electrodes.
Claim 4
Dependent Claim
19 words
The cell recited in claim 2, wherein said three gate electrodes together form a structural continuum over said channel.
Claim 5
Dependent Claim
70 words
The cell recited in claim 3, wherein said memory means and said field effect transistor gate electrodes are symmetrically disposed with respect to said first and second conductive regions in said substrate, said memory means gate electrode is heavily doped polycrystalline silicon, and said memory means gate electrode is coextensive with and in immediate contact with a silicon nitride layer located between said memory means gate electrode and said channel.
Claim 6
Dependent Claim
37 words
The cell recited in claim 4, wherein said substrate channel dopant concentration in the proximity of said first and second transistor electrodes differs from said substrate channel dopant concentration in the proximity of said memory means electrode.
Claim 7
Dependent Claim
42 words
The cell recited in claim 5, wherein said memory means is a nonvolatile alterable threshold transistor, said field effect transistors are n-channel devices, and the signal on said memory line has a nominal magnitude of 20 volts and duration of 1 millisecond.
Claim 8
Dependent Claim
29 words
The cell recited in claim 1, wherein the voltages coupled to said gate and first conductive path electrodes of said first field effect transistor are substantially equal in mangitude.
Claim 9
Dependent Claim
55 words
The cell recited in claim 1 or 7, wherein the voltage coupled to said gate electrode of said memory means is substantially greater in relative magnitude than either of the voltages coupled to said gate and first conductive path electrodes of said first field effect transistor, and is comprised of a sequence of multiple pulses.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-04-18 | 1986-10-18 | 1987-04-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-04-18 | 1990-10-18 | 1991-04-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-04-18 | 1994-10-18 | 1995-04-19 | $7700.00 | Window Closed / Lapsed |