US5299152A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Anti-fuse memory device with switched capacitor setting method
Assignee: Sharp Corp
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Filing: 1992-01-28
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Granted: 1994-03-29
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Expires: 2012-01-28
Abstract
Abstract A semiconductor device includes memory cells each of which include a plurality of groups of an anti-fuse and a transistor connected in series; a capacitor including first and second electrodes, with the first electrode connected to a bit line of the memory cell; a first switch connected between the bit line and a power source; a second switch connected between the power source and the second electrode of the capacitor; and a third switch connected between the second electrode of the capacitor and a ground. A specific memory cell is selected out of the memory cells, and a superposed supply voltage is applied through the capacitor to the anti-fuse of the specific memory by turning on and/or off the first through third switches, so that a storage of information in the memory cell can be performed.
Inventors
- 👤 Hiroshi Ishihara
- 👤 Kenichi Tanaka
- 👤 Keizo Sakiyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:28
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
161 words
A method of making a conduction by breaking down an anti-fuse in a semiconductor device that includes a plurality of anti-fuses and a capacitance with one capacitance electrode being connected to first terminals of the anti-fuses, the method comprising the steps of: turning on a transistor connected between a second terminal of a specific anti-fuse and a basic potential for selecting the specific anti-fuse out of the plurality of anti-fuse; impressing a first potential which have predetermined potential difference on one capacitance electrode and the first terminal of the specific anti-fuse, and setting the ground level on the other capacitance electrode so as to charge the one capacitance electrode, cutting off the first potential, and impressing a second potential on the other capacitance electrode, thereby the first potential and the second potential being superposed on one capacitance electrode, applying the superposed potential to the first terminal of the specific anti-fuse to execute a conduction by the breakdown of the specific anti-fuse.
Claim 2
Independent Claim
161 words
A method of making a conduction by breaking down an anti-fuse in a semiconductor device that includes a plurality of anti-fuses and a capacitance with one capacitance electrode being connected to first terminals of the anti-fuses, the method comprising the steps of: turning on a transistor connected between a second terminal of a specific anti-fuse and a basic potential for selecting the specific anti-fuse out of the plurality of anti-fuse; impressing a first potential which have predetermined potential difference on one capacitance electrode and the first terminal of the specific anti-fuse, and setting the ground level on the other capacitance electrode so as to charge the one capacitance electrode, cutting off the first potential, and impressing a second potential on the other capacitance electrode, thereby the first potential and the second potential being superposed on one capacitance electrode, applying the superposed potential to the first terminal of the specific anti-fuse to execute a conduction by the breakdown of the specific anti-fuse.
Claim 3
Dependent Claim
18 words
A method as claimed in claim 1, wherein the first and second potentials are of the same polarity.
Claim 4
Dependent Claim
21 words
A method as claimed in claim 1, wherein the first and second potentials are the same voltage as the power source.
Claim 5
Dependent Claim
36 words
A method as claimed in claim 1, wherein a combination of the anti-fuse and the transistor forms a unit memory cell, and the breakdown of one anti-fuse performs the storage of information into a memory cell.
Claim 6
Dependent Claim
15 words
A method as claimed in claim 1, wherein the basic potential is a ground level.
References Cited (Backward Citations)
US4899205A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-03-28 | 1997-09-27 | 1998-03-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-28 | 2001-09-27 | 2002-03-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-28 | 2005-09-27 | 2006-03-29 | $7700.00 | Window Closed / Lapsed |