Method of making a 3-dimensional programmable antifuse for integrated circuits

Claim 1

A process to form a programmable 3-dimensional antifuse element in a integrated circuit fabricated on a starting substrate, said process comprising: a) forming a isolative dielectric layer over an existing surface of said starting substrate, said starting substrate surface having first and second conductors therein; b) masking and etching a first buried contact opening thereby exposing a portion of said first conductor; c) placing a first conductive material superjacent said isolative dielectric layer and said first conductor's exposed portion thereby forming a first buried contact between said first conductive material and said first conductor's exposed portion; d) patterning said first conductive material thereby leaving a patterned portion of said first conductive material aligned about said first buried contact; e) forming a dielectric layer superjacent said patterned first conductive material and said isolative dielectric layer; f) masking and etching a second buried contact opening thereby exposing a portion of said second conductor; g) placing a second conductive material superjacent said dielectric layer and said second conductor's exposed portion thereby forming a second buried contact between said second conductive material and said second conductor's exposed portion; and h) patterning said second conductive material thereby leaving a patterned portion of said second conductive material aligned about said second buried contact and extending to and overlying the patterned portion of said first conductive material; wherein said patterned first conductive material, the portion of said patterned second conductive material overlying said first patterned conductive material and the portion of said dielectric residing therebetween form said programmable 3-dimensional antifuse structure.