US6078100A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Utilization of die repattern layers for die internal connections
Assignee: Micron Technology Inc
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Filing: 1999-01-13
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Granted: 2000-06-20
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Expires: 2019-01-13
Abstract
Abstract The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball or bump sites are in electrical communication with external communication traces which are used to route signals from the flip-chip integrated circuitry. Such external communication traces generally result in unused space on the exterior surface of the flip-chip. This unused space can be utilized for forming routing traces to connect portions of the internal circuitry of the flip-chip rather than forming such routing traces internally, for forming routing traces to connect two or more semiconductor dice, or for forming routing traces for use as repair mechanisms.
Inventors
- 👤 Kevin G. Duesman
- 👤 Warren M. Farnworth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 11:04
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W72/00; H10W72/01; H10W72/012
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
93 words
A semiconductor device, comprising: a semiconductor chip having at least one active surface; a plurality of external communication traces on said semiconductor chip active surface, wherein each of said external communication traces direct signals between internal circuitry of said semiconductor chip and a site on said semiconductor chip active surface for connection with external components; at least one routing trace, extending between two circuit portions of said semiconductor chip, on an area of said active surface unoccupied by said external communication traces, wherein said at least one routing trace comprises a repair mechanism.
Claim 2
Dependent Claim
93 words
A semiconductor device, comprising: a semiconductor chip having at least one active surface; a plurality of external communication traces on said semiconductor chip active surface, wherein each of said external communication traces direct signals between internal circuitry of said semiconductor chip and a site on said semiconductor chip active surface for connection with external components; at least one routing trace, extending between two circuit portions of said semiconductor chip, on an area of said active surface unoccupied by said external communication traces, wherein said at least one routing trace comprises a repair mechanism.
Claim 3
Dependent Claim
34 words
The semiconductor device of claim 1, wherein said repair mechanism is adapted to be activated by severance of said at least one routing trace to activate a selected internal circuit in said semiconductor chip.
Claim 4
Dependent Claim
34 words
The semiconductor device of claim 1, wherein said repair mechanism is adapted to be activated by severance of said at least one routing trace to deactivate a selected internal circuit in said semiconductor chip.
Claim 5
Dependent Claim
110 words
A semiconductor device, comprising: a semiconductor chip having at least one active surface; a plurality of external communication traces within a plane over on said semiconductor chip active surface; wherein each of said external communication traces is adapted to direct signals between internal circuitry of said semiconductor chip and a site on said semiconductor chip active surface for connection with external components; and at least one routing trace carried over an area of said active surface and lying within the same plane as said external communication traces and laterally spaced therefrom, said routing trace connecting a first internal circuit component to a second internal circuit component of said semiconductor chip.
Claim 6
Dependent Claim
110 words
A semiconductor device, comprising: a semiconductor chip having at least one active surface; a plurality of external communication traces within a plane over on said semiconductor chip active surface; wherein each of said external communication traces is adapted to direct signals between internal circuitry of said semiconductor chip and a site on said semiconductor chip active surface for connection with external components; and at least one routing trace carried over an area of said active surface and lying within the same plane as said external communication traces and laterally spaced therefrom, said routing trace connecting a first internal circuit component to a second internal circuit component of said semiconductor chip.
Claim 7
Dependent Claim
97 words
A semiconductor device, comprising: a semiconductor chip having at least one active surface; a plurality of external communication traces over said semiconductor chip active surface; wherein each of said external communication traces is adapted to direct signals between internal circuitry of said semiconductor chip and a site on said semiconductor chip active surface for connection with external components; and at least one routing trace carried over said active surface in an area unoccupied by said external communication traces, said routing trace connecting a first internal circuit component to a second internal circuit component of said semiconductor chip.
Claim 8
Dependent Claim
97 words
A semiconductor device, comprising: a semiconductor chip having at least one active surface; a plurality of external communication traces over said semiconductor chip active surface; wherein each of said external communication traces is adapted to direct signals between internal circuitry of said semiconductor chip and a site on said semiconductor chip active surface for connection with external components; and at least one routing trace carried over said active surface in an area unoccupied by said external communication traces, said routing trace connecting a first internal circuit component to a second internal circuit component of said semiconductor chip.
Claim 9
Dependent Claim
100 words
A semiconductor device, comprising: a semiconductor chip having at least one active surface; a plurality of external communication traces over said semiconductor chip active surface; wherein each of said external communication traces is adapted to direct signals between internal circuitry of said semiconductor chip and a site on said semiconductor chip active surface for connection with external components; and at least one routing trace carried over an area of said active surface in laterally spaced relationship to said external communication traces, said routing trace connecting a first internal circuit component to a second internal circuit component of said semiconductor chip.
Claim 10
Dependent Claim
100 words
A semiconductor device, comprising: a semiconductor chip having at least one active surface; a plurality of external communication traces over said semiconductor chip active surface; wherein each of said external communication traces is adapted to direct signals between internal circuitry of said semiconductor chip and a site on said semiconductor chip active surface for connection with external components; and at least one routing trace carried over an area of said active surface in laterally spaced relationship to said external communication traces, said routing trace connecting a first internal circuit component to a second internal circuit component of said semiconductor chip.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-20 | 2003-12-20 | 2004-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-20 | 2007-12-20 | 2008-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-20 | 2011-12-20 | 2012-06-20 | $7700.00 | Window Closed / Lapsed |