Anti-fuse programming path

Claim 2

A programmable circuit providing a programmed signal in an integrated circuit comprising: a first node carrying the programmed signal; a first programming bus; a first anti-fuse including a first terminal coupled to the first node and a second terminal coupled to the first programming bus; and an anti-fuse programming pad coupled to the first programming bus for permitting a sufficient voltage to short the first anti-fuse to be applied to the first programming bus from external to the integrated circuit, wherein the anti-fuse programming pad is bonded to ground during assembly and packaging of the integrated circuit.

Claim 3

A programmable circuit providing a programmed signal in an integrated circuit comprising: a first node carrying the programmed signal; a first programming bus; a first anti-fuse including a first terminal coupled to the first node and a second terminal coupled to the first programming bus; an anti-fuse programming pad coupled to the first programming bus for permitting a sufficient voltage to short the first anti-fuse to be applied to the first programming bus from external to the integrated circuit; a second programming bus; a second anti-fuse including a first terminal coupled to the first node and a second terminal coupled to the second programming bus; and Vpop circuitry for supplying a sufficient voltage to short the second anti-fuse to the second programming bus from internal to the integrated circuit.

Claim 4

A programmable circuit providing a programmed signal in an integrated circuit comprising: a first node carrying the programmed signal; a first programming bus; a first anti-fuse including a first terminal coupled to the first node and a second terminal coupled to the first programming bus; an anti-fuse programming pad coupled to the first programming bus for permitting a sufficient voltage to short the first anti-fuse to be applied to the first programming bus from external to the integrated circuit; a second programming bus; a second anti-fuse including a first terminal coupled to the first node and a second terminal coupled to the second programming bus; and Vpop circuitry for supplying a sufficient voltage to short the second anti-fuse to the second programming bus from internal to the integrated circuit.

Claim 5

The programmable circuit of claim 2 further comprising: a control pad coupled to the Vpop circuitry for permitting external control of when the sufficient voltage to short the second anti-fuse is supplied from the Vpop circuitry.

Claim 6

The programmable circuit of claim 2 wherein the Vpop circuitry forces the second programming bus to a selected voltage if the sufficient voltage to short the first anti-fuse is applied to the first programming bus from external to the integrated circuit via the anti-fuse programming pad.

Claim 7

An integrated circuit comprising: a first node carrying a programmed signal; a first programming bus; a first anti-fuse including a first terminal coupled to the first node and a second terminal coupled to the first programming bus; and an anti-fuse programming pad coupled to the first programming bus for permitting a sufficient voltage to short the first anti-fuse to be applied to the first programming bus from external to the integrated circuit, wherein the anti-fuse programming pad is bonded to ground during assembly and packaging of the integrated circuit.

Claim 8

An integrated circuit comprising: a first node carrying a programmed signal; a first programming bus; a first anti-fuse including a first terminal coupled to the first node and a second terminal coupled to the first programming bus; and an anti-fuse programming pad coupled to the first programming bus for permitting a sufficient voltage to short the first anti-fuse to be applied to the first programming bus from external to the integrated circuit, wherein the anti-fuse programming pad is bonded to ground during assembly and packaging of the integrated circuit.

Claim 9

An integrated circuit comprising: a first node carrying a programmed signal; a first programming bus; a first anti-fuse including a first terminal coupled to the first node and a second terminal coupled to the first programming bus; an anti-fuse programming pad coupled to the first programming bus for permitting a sufficient voltage to short the first anti-fuse to be applied to the first programming bus from external to the integrated circuit; a second programming bus; a second anti-fuse including a first terminal coupled to the first node and a second terminal coupled to the second programming bus; and Vpop circuitry for supplying a sufficient voltage to short the second anti-fuse to the second programming bus from internal to the integrated circuit.

Claim 10

An integrated circuit comprising: a first node carrying a programmed signal; a first programming bus; a first anti-fuse including a first terminal coupled to the first node and a second terminal coupled to the first programming bus; an anti-fuse programming pad coupled to the first programming bus for permitting a sufficient voltage to short the first anti-fuse to be applied to the first programming bus from external to the integrated circuit; a second programming bus; a second anti-fuse including a first terminal coupled to the first node and a second terminal coupled to the second programming bus; and Vpop circuitry for supplying a sufficient voltage to short the second anti-fuse to the second programming bus from internal to the integrated circuit.

Claim 11

The integrated circuit of claim 6 further comprising: a control pad coupled to the Vpop circuitry for permitting external control of when the sufficient voltage to short the second anti-fuse is supplied from the Vpop circuitry.

Claim 12

The integrated circuit of claim 6 wherein the Vpop circuitry forces the second programming bus to a selected voltage if the sufficient voltage to short the first anti-fuse is applied to the first programming bus from external to the integrated circuit via the anti-fuse programming pad.

Claim 13

The integrated circuit of claim of claim 6 further comprising circuitry for indicating whether the first anti-fuse is shorted during wafer or probe testing.

Claim 14

An integrated circuit comprising: a first node carrying a programmed signal; a first programming bus; a first anti-fuse including a first terminal coupled to the first node and a second terminal coupled to the first programming bus; an anti-fuse programming pad coupled to the first programming bus for permitting a sufficient voltage to short the first anti-fuse to be applied to the first programming bus from external to the integrated circuit, wherein the integrated circuit includes a fuse identification based on the state of the programmed signal.

Claim 15

An integrated circuit comprising: a first node carrying a programmed signal; a first programming bus; a first anti-fuse including a first terminal coupled to the first node and a second terminal coupled to the first programming bus; an anti-fuse programming pad coupled to the first programming bus for permitting a sufficient voltage to short the first anti-fuse to be applied to the first programming bus from external to the integrated circuit, wherein the integrated circuit includes a fuse identification based on the state of the programmed signal.

Claim 16

An integrated circuit comprising: a first node carrying a programmed signal; a first programming bus; a first anti-fuse including a first terminal coupled to the first node and a second terminal coupled to the first programming bus; and an anti-fuse programming pad coupled to the first programming bus for permitting a sufficient voltage to short the first anti-fuse to be applied to the first programming bus from external to the integrated circuit, wherein the integrated circuit includes a mode of operation based on the state the programmed signal.

Claim 17

An integrated circuit comprising: a first node carrying a programmed signal; a first programming bus; a first anti-fuse including a first terminal coupled to the first node and a second terminal coupled to the first programming bus; and an anti-fuse programming pad coupled to the first programming bus for permitting a sufficient voltage to short the first anti-fuse to be applied to the first programming bus from external to the integrated circuit, wherein the integrated circuit includes a mode of operation based on the state the programmed signal.

Claim 22

The method of claim 13 wherein the first programming voltage is applied during wafer or probe testing of the integrated circuit.

Claim 23

The method of claim 13 wherein the second programming voltage is applied after the integrated circuit is packaged.

Claim 24

The method of claim 13 further comprising the step of: controlling, from external to the integrated circuit, the internal application of the second programming voltage.

Claim 25

The method of claim 13 further comprising the step of: forcing the second programming bus to a selected voltage if the first programming voltage is applied to the first programming bus from external to the integrated circuit via the anti-fuse programming pad.

Claim 26

The method of claim 13 further comprising the step of: indicating whether the first anti-fuse is shorted during wafer or probe testing.

Claim 27

The method of claim 13 further comprising the step of: bonding the first programming pad to ground prior to or during the packaging of the integrated circuit.

Claim 28

An integrated circuit receiving n address bits and comprising: primary circuit elements being selectable by binary values of the n address bits; redundant circuit elements; and match anti-fuse circuits corresponding to the redundant circuit elements, each match anti-fuse circuit comprising: a plurality of programmable circuits, each providing a programmed signal corresponding to one of the possible binary values of at least one of the n address bits, wherein each programmable circuit is responsive to a binary value of the at least one of the n address bits to activate the programmed signal when the binary value of the at least one of the n address bits corresponds to the programmed signal, each programmable circuit including: a first node carrying the programmed signal, a first programming bus, a first anti-fuse including a first terminal coupled to the first node and a second terminal coupled to the first programming bus, and an anti-fuse programming pad coupled to the first programming bus for permitting a sufficient voltage to short the first anti-fuse to be applied to the first programming bus from external to the integrated circuit; and a compare circuit coupled to the plurality of programmable circuits for activating a match signal in response to all of the programmed signals being active, wherein the activated match signal is used to disable a primary circuit element from being selected by a corresponding binary value of the n address bits and to enable the redundant circuit element to be selected by the corresponding binary value of the n address bits.

Claim 29

An integrated circuit receiving n address bits and comprising: primary circuit elements being selectable by binary values of the n address bits; redundant circuit elements; and match anti-fuse circuits corresponding to the redundant circuit elements, each match anti-fuse circuit comprising: a plurality of programmable circuits, each providing a programmed signal corresponding to one of the possible binary values of at least one of the n address bits, wherein each programmable circuit is responsive to a binary value of the at least one of the n address bits to activate the programmed signal when the binary value of the at least one of the n address bits corresponds to the programmed signal, each programmable circuit including: a first node carrying the programmed signal, a first programming bus, a first anti-fuse including a first terminal coupled to the first node and a second terminal coupled to the first programming bus, and an anti-fuse programming pad coupled to the first programming bus for permitting a sufficient voltage to short the first anti-fuse to be applied to the first programming bus from external to the integrated circuit; and a compare circuit coupled to the plurality of programmable circuits for activating a match signal in response to all of the programmed signals being active, wherein the activated match signal is used to disable a primary circuit element from being selected by a corresponding binary value of the n address bits and to enable the redundant circuit element to be selected by the corresponding binary value of the n address bits.

Claim 30

The integrated circuit of claim 20 wherein the anti-fuse programming pad is bonded to ground during assembly and packaging of the integrated circuit.

Claim 31

The integrated circuit of claim 20 wherein each programmable circuit includes: a second programming bus; a second anti-fuse including a first terminal coupled to the first node and a second terminal coupled to the second programming bus; and Vpop circuitry for supplying a sufficient voltage to short the second anti-fuse to the second programming bus from internal to the integrated circuit.

Claim 32

The integrated circuit of claim 22 further comprising: a control pad coupled to the Vpop circuitry for permitting external control of when the sufficient voltage to short the second anti-fuse is supplied from the Vpop circuitry.

Claim 33

The integrated circuit of claim 22 wherein the Vpop circuitry forces the second programming bus to a selected voltage if the sufficient voltage to short the first anti-fuse is applied to the first programming bus from external to the integrated circuit via the anti-fuse programming pad.

Claim 34

The integrated circuit of claim of claim 22 further comprising circuitry for indicating whether the first anti-fuse is shorted during wafer or probe testing.

Claim 35

The integrated circuit of claim 20 wherein the integrated circuit is a memory integrated circuit comprising an array of memory cells arranged in rows and columns, and wherein the primary circuit elements comprise rows of memory cells.

Claim 36

The integrated circuit of claim 20 wherein the integrated circuit is a memory integrated circuit comprising an array of memory cells arranged in rows and columns, and wherein the primary circuit elements comprise columns of memory cells.

Claim 37

The integrated circuit of claim 20 wherein the integrated circuit is a memory integrated circuit comprising an array of memory cells arranged in rows and columns, and wherein the primary circuit elements comprise rows and columns of memory cells.

Claim 38

The integrated circuit of claim 20 wherein the integrated circuit is a dynamic random access memory (DRAM).