US5677888A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Redundancy circuit for programmable integrated circuits
Assignee: Renesas Electronics America Inc
•
Filing: 1995-06-06
•
Granted: 1997-10-14
•
Expires: 2015-06-06
Abstract
Abstract An antifuse redundancy circuit operates with transparency to external circuitry and users. In one embodiment, an antifuse redundancy circuit incorporates two antifuses rather than one. The circuit is arranged so that both antifuses may be simultaneously programmed and read. If a single antifuse is programmed without programming the other antifuse, the antifuse redundancy circuit will register a programmed antifuse. Additionally, if a single programmed antifuse is unintentionally deprogrammed after both antifuses in the redundancy circuit have been programmed, the antifuse redundancy circuit will continue to register a programmed antifuse. The result is both an increase in manufacturing yield and an increase in the reliability of integrated circuits utilizing antifuses.
Inventors
- 👤 Sik K. Lui
- 👤 Raymond M. Chu
- 👤 David J. Pilling
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:28
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/781; G06; G06F; G06F11/00; G11C17/00; G11C17/14; G11C17/16; G11C17/18; G11C29/785; Y; Y10; Y10S; Y10S257/00; Y10S257/919
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
263 words
A circuit comprising: a first antifuse; a second antifuse; an output node; a program circuit for coupling a programming voltage across the first and second antifuses, the program circuit including: a program terminal; a voltage bias circuit having a control terminal coupled to the program terminal and having a voltage node; a first PMOS transistor having a source coupled to a first voltage source, a drain coupled to a terminal of the first antifuse, and a gate coupled to the program terminal; and a first NMOS transistor having a source coupled to a second voltage source, a drain coupled to the second antifuse, and a gate coupled to the voltage node of the voltage bias circuit, wherein the voltage bias circuit includes: a second PMOS transistor having a source coupled to the first voltage source, a drain coupled to the voltage node, and a gate coupled to the program terminal; a second NMOS transistor having a drain and a gate coupled to the voltage node and having a source; and a third NMOS transistor having a drain and a gate coupled to the second NMOS transistor source and having a source coupled to the second voltage source; a read circuit for coupling a read voltage across the first and second antifuses and for coupling the first and second antifuses to the output node; wherein when at least one of the first and second antifuses is programmed, the circuit is in a programmed state, the programmed state being the same when either the first antifuse, the second anti fuse or both antifuses are programmed.
Claim 2
Dependent Claim
263 words
A circuit comprising: a first antifuse; a second antifuse; an output node; a program circuit for coupling a programming voltage across the first and second antifuses, the program circuit including: a program terminal; a voltage bias circuit having a control terminal coupled to the program terminal and having a voltage node; a first PMOS transistor having a source coupled to a first voltage source, a drain coupled to a terminal of the first antifuse, and a gate coupled to the program terminal; and a first NMOS transistor having a source coupled to a second voltage source, a drain coupled to the second antifuse, and a gate coupled to the voltage node of the voltage bias circuit, wherein the voltage bias circuit includes: a second PMOS transistor having a source coupled to the first voltage source, a drain coupled to the voltage node, and a gate coupled to the program terminal; a second NMOS transistor having a drain and a gate coupled to the voltage node and having a source; and a third NMOS transistor having a drain and a gate coupled to the second NMOS transistor source and having a source coupled to the second voltage source; a read circuit for coupling a read voltage across the first and second antifuses and for coupling the first and second antifuses to the output node; wherein when at least one of the first and second antifuses is programmed, the circuit is in a programmed state, the programmed state being the same when either the first antifuse, the second anti fuse or both antifuses are programmed.
Claim 3
Dependent Claim
25 words
The circuit as in claim 1 further comprising: a discharge circuit coupled between the gate of the second NMOS transistor and a third voltage source.
Claim 4
Dependent Claim
237 words
A circuit comprising; a first antifuse; a second anti fuse; an output node; a program circuit for coupling a programming voltage across the first and second antifuses; a read circuit for coupling a read voltage across the first and second anti fuses and for coupling the first and second antifuses to the output node, the read circuit including: a READ terminal; a FUSE -- OUT terminal; a READ OUTPUT node coupled to a terminal of the first antifuse; a first PMOS transistor having a source coupled to a first voltage source, a drain coupled to the READ OUTPUT node, and a gate coupled to the READ terminal; a second PMOS transistor having a source coupled to the READ OUTPUT node, a drain coupled to the FUSE -- OUT terminal, and a gate coupled to the READ terminal; a first NMOS transistor having a gate coupled to the READ OUTPUT node, a source coupled to a second voltage source, and a drain coupled to the second antifuse; and a second NMOS transistor having a gate coupled to the first NMOS transistor drain, a drain coupled to the READ OUTPUT node, and a source coupled to the second voltage source; wherein when at least one of the first and second antifuses is programmed, the circuit is in a programmed state, the programmed state being the same when either the first antifuse, the second antifuse or both antifuses are programmed.
Claim 5
Dependent Claim
237 words
A circuit comprising; a first antifuse; a second anti fuse; an output node; a program circuit for coupling a programming voltage across the first and second antifuses; a read circuit for coupling a read voltage across the first and second anti fuses and for coupling the first and second antifuses to the output node, the read circuit including: a READ terminal; a FUSE -- OUT terminal; a READ OUTPUT node coupled to a terminal of the first antifuse; a first PMOS transistor having a source coupled to a first voltage source, a drain coupled to the READ OUTPUT node, and a gate coupled to the READ terminal; a second PMOS transistor having a source coupled to the READ OUTPUT node, a drain coupled to the FUSE -- OUT terminal, and a gate coupled to the READ terminal; a first NMOS transistor having a gate coupled to the READ OUTPUT node, a source coupled to a second voltage source, and a drain coupled to the second antifuse; and a second NMOS transistor having a gate coupled to the first NMOS transistor drain, a drain coupled to the READ OUTPUT node, and a source coupled to the second voltage source; wherein when at least one of the first and second antifuses is programmed, the circuit is in a programmed state, the programmed state being the same when either the first antifuse, the second antifuse or both antifuses are programmed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-13 | 2001-04-14 | 2001-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-13 | 2005-04-14 | 2005-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-13 | 2009-04-14 | 2009-10-14 | $7700.00 | Window Closed / Lapsed |