US5424672A
Expired / Lapsed
US
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Low current redundancy fuse assembly
Assignee: Micron Technology Inc
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Filing: 1994-02-24
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Granted: 1995-06-13
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Expires: 2014-02-24
Abstract
Abstract In a microcircuit device such as a memory chip, where a bank of fuse-controlled latch pulse routing-circuits are used to program redundant circuits or other programming options with every memory cycle or multiple thereof, the amount of current drawn by every fuse-control circuit is reduced by controlling each bank of circuits with a bank-enabling, fuse-programmed circuit between the latch pulse source and the bank of fuse-controlled programming circuits, and by adding a second fuse into each programming circuit; whereby, the bank of programing circuits can be enabled by alternately blowing one of two fuses in the bank-enabling circuit, and each programming logic can set by alternately blowing one of its pair of fuses thus cutting off any current path through the programming circuit regardless of the programming state of the circuit.
Inventors
- 👤 Timothy B. Cowles
- 👤 Steven G. Renfro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:06
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/785; G11C29/787; G11C29/83; G11C29/832; H; H03; H03K; H03K19/00; H03K19/003; H03K19/00392; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
271 words
In a microcircuit device comprising a bank of at least two programming logic circuits, wherein each of said logic circuits includes a first fuse in series with a switching transistor, and a control line connected to the node between said first fuse and said switching transistor, and wherein a latch pulse source is wired to a control terminal of said switching transistor in order to generate on said control line a logic level representative of the status of said first fuse; an improvement for reducing the current drawn through said first fuse which comprises: in each of said programming logic circuit, a second fuse wired in series with said first fuse between said node and said switching transistor; and a bank-enabling circuit wired between said latch pulse source and a control terminal of the switching transistor of each of said logic circuits, said bank-enabling circuit comprising: a bank switching transistor and two bank fuses wired in series therewith, wherein said bank switching transistor has a control terminal connected to said latch pulse source, a first current-carrying terminal connected to a first pole of a supply voltage, a second current-carrying terminal wired to a first terminal of a first of said bank fuses; and a second of said bank fuses has a first terminal connected to a second terminal of said first bank fuse and a second terminal connected to an opposite pole of said supply voltage; whereby the burning of said first bank fuse disables said logic circuits, and the burning of said second bank fuse allows the passage of a latch pulse through said bank-enabling circuit toward said logic circuits.
Claim 2
Dependent Claim
271 words
In a microcircuit device comprising a bank of at least two programming logic circuits, wherein each of said logic circuits includes a first fuse in series with a switching transistor, and a control line connected to the node between said first fuse and said switching transistor, and wherein a latch pulse source is wired to a control terminal of said switching transistor in order to generate on said control line a logic level representative of the status of said first fuse; an improvement for reducing the current drawn through said first fuse which comprises: in each of said programming logic circuit, a second fuse wired in series with said first fuse between said node and said switching transistor; and a bank-enabling circuit wired between said latch pulse source and a control terminal of the switching transistor of each of said logic circuits, said bank-enabling circuit comprising: a bank switching transistor and two bank fuses wired in series therewith, wherein said bank switching transistor has a control terminal connected to said latch pulse source, a first current-carrying terminal connected to a first pole of a supply voltage, a second current-carrying terminal wired to a first terminal of a first of said bank fuses; and a second of said bank fuses has a first terminal connected to a second terminal of said first bank fuse and a second terminal connected to an opposite pole of said supply voltage; whereby the burning of said first bank fuse disables said logic circuits, and the burning of said second bank fuse allows the passage of a latch pulse through said bank-enabling circuit toward said logic circuits.
Claim 3
Dependent Claim
40 words
The improvement of claim 1, wherein said opposite pole of said supply voltage comprises a circuit ground reference, and said first fuse of each of said logic circuits has a terminal connected to said first pole of a supply voltage.
Claim 4
Dependent Claim
24 words
The improvement of claim 2, wherein each of said logic circuits further comprises a programming driver having an input connected to said control line.
Claim 5
Dependent Claim
38 words
The improvement of claim 2, wherein said bank-enabling circuit further comprises a current driver having an input terminal connected between said bank fuses and an output terminal connected to the control terminal of each of said logic circuits.
Claim 6
Dependent Claim
19 words
The improvement of claim 1, wherein said bank of logic circuits is connected to an array of microcircuit devices.
Claim 7
Dependent Claim
18 words
The improvement of claim 1, wherein said bank of logic circuits is connected to a microcircuit memory array.
Claim 8
Independent Claim
153 words
A method for reducing the amount of current drawn by a bank of programming circuits wherein each circuit includes a current transmitting device mounted in series with a first fuse between the poles of a supply voltage, said method comprising: adding an extra one of said programming circuits to said bank as a bank-enabling circuit; in each one of said programming circuits and said bank-enabling circuit, adding a second fuse between said first fuse and said device; programming each of said programming circuits and said bank-enabling circuit by alternately blowing one of said first and second fuses; driving each of said programming circuits with a signal taken at a point between said first and second fuses in said extra-one of said circuit; and using a signal taken between said first and second fuse in each of said programming circuits as an output indicative of the status of the fuses in said programming circuit.
Claim 9
Independent Claim
153 words
A method for reducing the amount of current drawn by a bank of programming circuits wherein each circuit includes a current transmitting device mounted in series with a first fuse between the poles of a supply voltage, said method comprising: adding an extra one of said programming circuits to said bank as a bank-enabling circuit; in each one of said programming circuits and said bank-enabling circuit, adding a second fuse between said first fuse and said device; programming each of said programming circuits and said bank-enabling circuit by alternately blowing one of said first and second fuses; driving each of said programming circuits with a signal taken at a point between said first and second fuses in said extra-one of said circuit; and using a signal taken between said first and second fuse in each of said programming circuits as an output indicative of the status of the fuses in said programming circuit.
Claim 10
Dependent Claim
34 words
The method of claim 7 which further comprises using a transistor as said current transmitting device, and applying an interrogating signal to a control input of said transistor in said extra-one of said circuit.
Claim 11
Independent Claim
61 words
A method for reducing the amount of current drawn through a blowable fuse associated with a programming logic circuit, which comprises: adding a second fuse in series with said blowable fuse; and setting said programming logic circuit by alternately blowing one of said fuses; and using a signal taken between said fuses as an indication of the status of said fuses.
Claim 12
Independent Claim
61 words
A method for reducing the amount of current drawn through a blowable fuse associated with a programming logic circuit, which comprises: adding a second fuse in series with said blowable fuse; and setting said programming logic circuit by alternately blowing one of said fuses; and using a signal taken between said fuses as an indication of the status of said fuses.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-12 | 1998-12-12 | 1999-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-12 | 2002-12-12 | 2003-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-12 | 2006-12-12 | 2007-06-13 | $7700.00 | Window Closed / Lapsed |