Cmos circuit with programmable input threshold

Claim 2

A CMOS circuit having an input threshold voltage, said CMOS circuit comprising: an input terminal; an output terminal; a first power supply terminal; a second power supply terminal; first field-effect transistor means having a source connected to said first power supply terminal, a drain connected to said output terminal, a gate connected to said input terminal, and a first channel means between said source and said drain having a first width and a first length; programmable field-effect transistor means having a gate terminal connected to said input terminal, a drain terminal connected to said output terminal, a source terminal connected to said second power supply terminal, second channel means between said drain terminal and said source terminal, said second channel means having an effective width and an effective length; and programmable input means connected to said second channel means for changing the ration of the product of said first width times said effective length to the product of said effective width times said first length said that the input threshold voltage of said CMOS circuit is changed responsive to the change of said ratio; wherein said second channel means includes a plurality of field-effect transistors connected in a series/parallel circuit; and wherein said programmable input means include gate terminal means connected to the gates of selected ones of said plurality of field-effect transistors such that said selected ones of said plurality of field-effect transistors may be turned on and off by electric signals applied to said gate terminal means.

Claim 3

The CMOS circuit of claim 1 further including register means for storing electrical signals, said register means having output means connected to said gate terminal means such that electrical signals may be applied via said gate terminal means to the gates of selected ones of said plurality of field-effect transistors.

Claim 4

The CMOS circuit of claim 2 wherein said first field-effect transistor means is a p channel device, and wherein said plurality of field-effect transistors of said second channel means are n channel devices.

Claim 5

The CMOS circuit of claim 3 wherein said second channel means comprises: a first n channel device having a source connected to said second power supply terminal, a drain connected to said output terminal and a gate connected to said input terminal; second and third n channel devices connected in series; said second n channel device having a drain connected to said output terminal, a gate connected to said input terminal, and a source; and said third n channel device having a drain connected to the source of said second n channel device, a gate connected to said gate terminal means, and a source connected to said second power supply terminal such that a first programmed electrical signal from said gate means to the gate of said third n channel device turns on said third n channel device changing the effective width and length of said channel means.

Claim 6

The CMOS circuit of claim 4 wherein said second channel means further comprises: fourth and fifth n channel devices connected in series; said fourth n channel device having a drain connected to said output terminal, a gate connected to said input terminal, and a source; and said fifth n channel device having a drain connected to the source of said third n channel device, a gate connected to said gate terminal means, and a source connected to said second power supply terminal such that a second programmed electrical signal from said gate means to the gate of said fifth n channel device turns on said fifth n channel device changing the effective width and length of said channel means.

Claim 7

A CMOS circuit having an input threshold voltage, said CMOS circuit comprising: an input terminal; an output terminal; a first power supply terminal; a second power supply terminal; first field-effect transistor means having a source connected to said first power supply terminal, a drain connected to said output terminal, a gate connected to said input terminal, and a first channel means between said source and said drain having a first width and a first length; programmable field-effect transistor means having a gate terminal connected to said input terminal, a drain terminal connected to said output terminal, a source terminal connected to said second power supply terminal, second channel means between said drain terminal and said source terminal, said second channel means having an effective width and an effective length; and programmable input means connected to said second channel means for changing the ratio of the product of said first width times said effective length to the product of said effective width times said first length such that the input threshold voltage of said CMOS circuit is changed responsive to the change of said ratio; wherein said first field-effect transistor means is a p channel device; said second channel means comprises a first n channel device having a source connected to said second power supply terminal, a gate connected to said input terminal, and a drain connected to said output terminal; a second n channel device having a source connected to said second power supply terminal, a gate, and a drain; and said programmable input means comprises a first jumper means connected between the drain of second n channel device and said output terminal and a second jumper means connected between the gate of said n channel device and said input terminal such that said second n channel device is included in said second channel means parallel to said first n channel device by said first and second jumper means.

Claim 8

A CMOS circuit having an input threshold voltage, said CMOS circuit comprising: an input terminal; an output terminal; a first power supply terminal; a second power supply terminal; first field-effect transistor means having a source connected to said first power supply terminal, a drain connected to said output terminal, a gate connected to said input terminal, and a first channel means between said source and said drain having a first width and a first length; programmable field-effect transistor means having a gate terminal connected to said input terminal, a drain terminal connected to said output terminal, a source terminal connected to said second power supply terminal, second channel means between said drain terminal and said source terminal, said second channel means having an effective width and an effective length; and programmable input means connected to said second channel means for changing the ratio of the product of said first width times said effective length to the product of said effective width times said first length such that the input threshold voltage of said CMOS circuit is changed responsive to the change of said ratio; wherein said first field-effect transistor means is a p channel device; said second channel means comprises a first n channel device having a source connected to said second power supply terminal, a gate connected to said input terminal, and a drain connected to said output terminal; a second n channel device having a source connected to said second power supply terminal, a gate, and a drain; and said programmable input means comprises a first jumper means connected between the drain of second n channel device and said output terminal and a second jumper means connected between the gate of said n channel device and said input terminal such that said second n channel device is included in said second channel means parallel to said first n channel device by said first and second jumper means.