US4584491A
Expired / Lapsed
US
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TTL to CMOS input buffer circuit for minimizing power consumption
Assignee: Motorola Solutions Inc
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Filing: 1984-01-12
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Granted: 1986-04-22
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Expires: 2004-01-12
Abstract
Abstract A buffer circuit comprising a current source transistor, a switching transistor and a current sink transistor coupled in series is provided. Control electrodes of the switching transistor and current sink transistor are directly connected and coupled to an input voltage. The buffer circuit has an accurate switchpoint voltage which is substantially process and temperature independent, and the circuit does not consume power for input voltages having low and high CMOS levels.
Inventors
- 👤 Richard W. Ulmer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:48
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0013; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948; H03K19/09482
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
225 words
A TTL to CMOS input buffer circuit for minimizing power consumption, comprising: a first MOS transistor of a first conductivity type having a first current electrode coupled to a terminal for receiving a supply voltage, and both a control electrode and a second current electrode connected together, for providing a reference current, said first MOS transistor being a depletion transistor; a second MOS transistor of a second conductivity type having a first current electrode coupled to the second current electrode of the first MOS transistor, a control electrode coupled to the single input, and a second current electrode coupled to an output terminal; and a third MOS transistor of the first conductivity type having a first current electrode coupled to the output terminal for providing an output voltage having CMOS voltage levels in response to the presence of an input voltage having TTL voltage levels at the single input, a control electrode connected directly to the control electrode of the second MOS transistor at the single input terminal, and a second current electrode coupled to a reference voltage, wherein the second MOS transistor is size ratioed with respect to the third MOS transistor so that the second MOS transistor is strongly conductive with respect to the third MOS transistor at a predetermined switchpoint voltage having a value between said power supply voltage and reference voltage.
Claim 2
Dependent Claim
225 words
A TTL to CMOS input buffer circuit for minimizing power consumption, comprising: a first MOS transistor of a first conductivity type having a first current electrode coupled to a terminal for receiving a supply voltage, and both a control electrode and a second current electrode connected together, for providing a reference current, said first MOS transistor being a depletion transistor; a second MOS transistor of a second conductivity type having a first current electrode coupled to the second current electrode of the first MOS transistor, a control electrode coupled to the single input, and a second current electrode coupled to an output terminal; and a third MOS transistor of the first conductivity type having a first current electrode coupled to the output terminal for providing an output voltage having CMOS voltage levels in response to the presence of an input voltage having TTL voltage levels at the single input, a control electrode connected directly to the control electrode of the second MOS transistor at the single input terminal, and a second current electrode coupled to a reference voltage, wherein the second MOS transistor is size ratioed with respect to the third MOS transistor so that the second MOS transistor is strongly conductive with respect to the third MOS transistor at a predetermined switchpoint voltage having a value between said power supply voltage and reference voltage.
Claim 3
Dependent Claim
20 words
The TTL to CMOS input buffer circuit of claim 1 wherein the first MOS transistor is an N-channel depletion transistor.
Claim 4
Dependent Claim
20 words
The TTL to CMOS input buffer circuit of claim 1 wherein the second MOS transistor is a P-channel enhancement transistor.
Claim 5
Dependent Claim
20 words
The TTL to CMOS input buffer circuit of claim 1 wherein the third MOS transistor is an N-channel enhancement transistor.
Claim 6
Dependent Claim
200 words
An inverting buffer circuit having a single input terminal for inverting an input voltage having TTL voltage levels to provide an inverted output signal having CMOS levels at an output terminal, and for consuming no power when receiving input voltages having CMOS levels, comprising: a high impedance current source means for providing an accurate reference current which is substantially independent of power supply variation; a first transistor of a first conductivity type having a first current electrode coupled to the current source means, a control electrode coupled to the input terminal, and a second current electrode coupled to the output terminal, for selectively coupling the current source means to the output terminal in response to the input voltage; and a second transistor of a second conductivity type having a first current electrode coupled to the second current electrode of the first transistor, a control electrode connected directly to the control electrode of the first transistor, and a second current electrode coupled to a reference voltage, wherein the first transistor is size ratioed with the second transistor so that the first transistor is strongly conductive compared to the second transistor when both transistors are biased at a predetermined trip point voltage.
Claim 7
Dependent Claim
200 words
An inverting buffer circuit having a single input terminal for inverting an input voltage having TTL voltage levels to provide an inverted output signal having CMOS levels at an output terminal, and for consuming no power when receiving input voltages having CMOS levels, comprising: a high impedance current source means for providing an accurate reference current which is substantially independent of power supply variation; a first transistor of a first conductivity type having a first current electrode coupled to the current source means, a control electrode coupled to the input terminal, and a second current electrode coupled to the output terminal, for selectively coupling the current source means to the output terminal in response to the input voltage; and a second transistor of a second conductivity type having a first current electrode coupled to the second current electrode of the first transistor, a control electrode connected directly to the control electrode of the first transistor, and a second current electrode coupled to a reference voltage, wherein the first transistor is size ratioed with the second transistor so that the first transistor is strongly conductive compared to the second transistor when both transistors are biased at a predetermined trip point voltage.
Claim 8
Dependent Claim
40 words
The inverting buffer circuit of claim 5 wherein the high impedance current source means is a third transistor of the second conductivity type, said third transistor being a depletion transistor having a first current electrode coupled to a supply voltage
Claim 9
Dependent Claim
113 words
A buffer circuit which minimizes power dissipation, comprising: high impedance current source means for providing a precise reference current which is substantially independent of power supply variations; transistor switching means coupled to the current source means for selectively coupling the current source means to an output terminal in response to an input signal; and transistor current sink means coupled to the switching means for selectively coupling the output terminal to a reference terminal in response to the input signal, wherein said transistor switching means are size ratioed with the transistor current sink means to make the transistor switching means strongly conductive compared to the transistor current sink means at a predetermined switchpoint voltage.
Claim 10
Dependent Claim
113 words
A buffer circuit which minimizes power dissipation, comprising: high impedance current source means for providing a precise reference current which is substantially independent of power supply variations; transistor switching means coupled to the current source means for selectively coupling the current source means to an output terminal in response to an input signal; and transistor current sink means coupled to the switching means for selectively coupling the output terminal to a reference terminal in response to the input signal, wherein said transistor switching means are size ratioed with the transistor current sink means to make the transistor switching means strongly conductive compared to the transistor current sink means at a predetermined switchpoint voltage.
Claim 11
Dependent Claim
48 words
The buffer circuit of claim 7 wherein the current source means comprise: a depletion type MOS transistor having a first current electrode coupled to a terminal for receiving a supply voltage, and a control electrode and a second current electrode connected together and coupled to the switching means.
Claim 12
Dependent Claim
47 words
The buffer circuit of claim 7 wherein the switching means comprise: an MOS transistor having a first current electrode coupled to the current source means, a control electrode connected to a terminal for receiving the input signal, and a second current electrode coupled to the output terminal.
Claim 13
Dependent Claim
51 words
The buffer circuit of claim 7 wherein the current sink means comprise: an MOS transistor having a first current electrode coupled to the switching means at the output terminal, a control electrode coupled to a terminal for receiving the input signal, and a second current electrode coupled to the reference terminal.
Claim 14
Dependent Claim
204 words
An input buffer circuit for minimizing power, comprising: a depletion MOS transistor having a first current electrode coupled to a terminal for receiving a supply voltage, and a control electrode connected to a second current electrode, for providing a reference current; a P-channel MOS transistor having a first current electrode coupled to the second current electrode of the depletion MOS transistor, a control electrode coupled to an input voltage terminal for receiving an input voltage, and a second current electrode coupled to an output terminal, for coupling the terminal receiving the supply voltage to the output terminal in response to the input voltage; and an N-channel MOS transistor having a first current electrode coupled to the second current electrode of the P-channel MOS transistor at the output terminal, a control electrode directly connected to the control electrode of the P-channel MOS transistor at the input voltage terminal, and a second current electrode coupled to a reference voltage terminal, for selectively coupling the reference terminal to the output terminal in response to the input voltage, said P-channel transistor having larger control electrode dimensions than said N-channel transistor so that said P-channel transistor is strongly conductive compared to said N-channel transistor at a predetermined switchpoint voltage.
Claim 15
Dependent Claim
204 words
An input buffer circuit for minimizing power, comprising: a depletion MOS transistor having a first current electrode coupled to a terminal for receiving a supply voltage, and a control electrode connected to a second current electrode, for providing a reference current; a P-channel MOS transistor having a first current electrode coupled to the second current electrode of the depletion MOS transistor, a control electrode coupled to an input voltage terminal for receiving an input voltage, and a second current electrode coupled to an output terminal, for coupling the terminal receiving the supply voltage to the output terminal in response to the input voltage; and an N-channel MOS transistor having a first current electrode coupled to the second current electrode of the P-channel MOS transistor at the output terminal, a control electrode directly connected to the control electrode of the P-channel MOS transistor at the input voltage terminal, and a second current electrode coupled to a reference voltage terminal, for selectively coupling the reference terminal to the output terminal in response to the input voltage, said P-channel transistor having larger control electrode dimensions than said N-channel transistor so that said P-channel transistor is strongly conductive compared to said N-channel transistor at a predetermined switchpoint voltage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-21 | 1989-10-21 | 1990-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-21 | 1993-10-21 | 1994-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-21 | 1997-10-21 | 1998-04-22 | $7700.00 | Window Closed / Lapsed |