US3980896A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit device
Assignee: Denso Corp
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Filing: 1975-04-09
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Granted: 1976-09-14
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Expires: 1995-04-09
Abstract
Abstract In an integrated circuit device with a propagation delay time almost independent of the fluctuation of the quality of the gate oxide layer and the fluctuation of power source voltage, a MOS logic element comprises a driving MOS transistor circuit including a p-channel or an n-channel enhancement type MOS transistor for a switching operation, and a load MOS transistor circuit, connected to said enhancement type MOS transistor and including an n-channel or a p-channel depletion type MOS transistor with a threshold voltage about two times higher than that of said enhancement type MOS transistor, for operating as a load of said driving MOS transistor circuit.
Inventors
- 👤 Mitsuharu Kato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:58
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948; H03K19/09482
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
84 words
An integrated circuit device including a MOS logic element in combination with a power source, wherein said MOS logic element comprises: a driving MOS transistor circuit including an enhancement type MOS transistor of a specific polarity, and a load MOS transistor circuit connected to said enhancement type MOS transistor and including a depletion type MOS transistor having its polarity opposite to that of said enhancement type MOS transistor with a threshold voltage about two times higher than that of said enhancement type MOS transistor.
Claim 2
Dependent Claim
84 words
An integrated circuit device including a MOS logic element in combination with a power source, wherein said MOS logic element comprises: a driving MOS transistor circuit including an enhancement type MOS transistor of a specific polarity, and a load MOS transistor circuit connected to said enhancement type MOS transistor and including a depletion type MOS transistor having its polarity opposite to that of said enhancement type MOS transistor with a threshold voltage about two times higher than that of said enhancement type MOS transistor.
Claim 3
Dependent Claim
59 words
An integrated circuit device as claimed in claim 1, wherein an odd number of inverters each of which comprises said MOS logic element are connected in series with an output terminal of said MOS logic element in the last stage connected to an input terminal of said MOS logic element in the first stage, thereby forming an oscillation circuit.
Claim 4
Dependent Claim
40 words
An integrated circuit device as claimed in claim 2, wherein a gate and a source of said depletion type MOS transistor are both connected to said power source and a drain thereof is connected to said driving MOS transistor circuit.
Claim 5
Dependent Claim
46 words
An integrated circuit device as claimed in claim 2, wherein a drain of said enhancement type MOS transistor is connected to said load MOS transistor circuit, a source thereof is connected to the ground potential and a gate thereof is constructed to receive an input signal.
Claim 6
Dependent Claim
52 words
An integrated circuit device as claimed in claim 2 further comprising: an output buffer circuit connected to said oscillation circuit for generating an output signal to be applied to a load in accordance with the output signal from said oscillation circuit, said buffer circuit effectively isolating said oscillation circuit from said load.
Claim 7
Dependent Claim
19 words
An integrated circuit device as claimed in claim 5 wherein said output buffer circuit comprises said MOS logic element.
Claim 8
Dependent Claim
40 words
An integrated circuit device as claimed in claim 1, wherein a gate and a source of said depletion type MOS transistor are both connected to said power source and a drain thereof is connected to said driving MOS transistor circuit.
Claim 9
Dependent Claim
46 words
An integrated circuit device as claimed in claim 1, wherein a drain of said enhancement type MOS transistor is connected to said load MOS transistor circuit, a source thereof is connected to the ground potential and a gate thereof is constructed to receive an input signal.
Claim 10
Dependent Claim
63 words
An integrated circuit device as claimed in claim 1, wherein said driving MOS transistor circuit comprises: a first and second enhancement type MOS transistors, both drains of which are connected to the same portion of said load MOS transistor circuit, and both sources of which are connected to the ground potential, and each gate of which is constructed to receive an input signal.
Claim 11
Dependent Claim
92 words
An integrated circuit device as claimed in claim 1, wherein said driving MOS transistor circuit comprises: a first enhancement type MOS transistor a drain of which is connected to said load MOS transistor circuit and a gate of which is constructed to receive an input signal, and a second enhancement type MOS transistor a drain of which is connected to a source of said first enhancement type MOS transistor and a source of which is connected to the ground potential and a gate of which is constructed to receive an input signal.
References Cited (Backward Citations)
US3700981A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-09-14 | 1980-03-15 | 1980-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-09-14 | 1984-03-15 | 1984-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-09-14 | 1988-03-15 | 1988-09-14 | $7700.00 | Window Closed / Lapsed |