US3700981A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit composed of cascade connection of inverter circuits
Assignee: Hitachi Ltd
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Filing: 1971-05-24
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Granted: 1972-10-24
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Expires: 1991-05-24
Abstract
Abstract A semiconductor device composed of cascade connected inverter circuits each comprising a load depletion type MIS transistor and a driving enhancement type MIS transistor. The semiconductor device can be properly operated by setting the threshold voltage of the load MIS transistors at a predetermined value, by selecting the dimensions and materials thereof.
Inventors
- 👤 Toshiaki Masuhara
- 👤 Minoru Nagata
- 👤 Masharu Kubo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:11
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09441; H03K19/09443; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/84; H10D84/83125
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
159 words
A semiconductor integrated circuit comprising a plurality of cascade connected inverter circuits each comprising a depletion mode MIS transistor having a drain electrode connected to a bias voltage source, a gate electrode, and a source electrode connected to said gate electrode, and operating in the saturation region of the drainvoltage-drain current characteristic thereof, and an enhancement mode MIS transistor having a drain electrode connected to said source electrode of said depletion mode transistor, a gate electrode connected to an input terminal for receiving an input signal, and a source electrode connected to a constant bias source, and operating in the triode region of the drain voltage-drain current characteristic thereof when an input signal is supplied to said input terminal, and wherein the dimensions of the transistors are selected so that the channel conductance Beta d and Beta l of each MIS transistor satisfies the following relationship with respect to the threshold voltage Vt of the depletion mode MIS transistor:
Claim 2
Dependent Claim
159 words
A semiconductor integrated circuit comprising a plurality of cascade connected inverter circuits each comprising a depletion mode MIS transistor having a drain electrode connected to a bias voltage source, a gate electrode, and a source electrode connected to said gate electrode, and operating in the saturation region of the drainvoltage-drain current characteristic thereof, and an enhancement mode MIS transistor having a drain electrode connected to said source electrode of said depletion mode transistor, a gate electrode connected to an input terminal for receiving an input signal, and a source electrode connected to a constant bias source, and operating in the triode region of the drain voltage-drain current characteristic thereof when an input signal is supplied to said input terminal, and wherein the dimensions of the transistors are selected so that the channel conductance Beta d and Beta l of each MIS transistor satisfies the following relationship with respect to the threshold voltage Vt of the depletion mode MIS transistor:
Claim 3
Dependent Claim
49 words
A semiconductor device according to claim 1, in which said threshold voltage Vt of said depletion mode MIS transistor further satisfies the relation: where q is the electron charge, epsilon s is the dielectric constant of the semiconductor substrate, and N is the impurity concentration in the semiconductor substrate.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-24 | 1976-04-24 | 1976-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-24 | 1980-04-24 | 1980-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-24 | 1984-04-24 | 1984-10-24 | $7700.00 | Window Closed / Lapsed |