US4016434A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Load gate compensator circuit
Assignee: International Business Machines Corp
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Filing: 1975-09-04
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Granted: 1977-04-05
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Expires: 1995-09-04
Abstract
Abstract An FET load gate compensator circuit is disclosed which compensates for variations in the parameters characterizing the silicon substrate in FET large scale integrated circuit device, by generating a compensatory load gate voltage to be applied to the load gates of the functional circuits therein.
Inventors
- 👤 Robert Joseph DeFilippi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 17:14
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/14; H03K17/145; H03K3/00; H03K3/01; H03K3/011; H03L; H03L1/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
228 words
In an integrated circuit on a semiconductor substrate, a load gate compensator circuit comprising: a first enhancement mode FET transistor in said substrate having its drain connected to a drain potential, its source connected to a first node, and its gate connected to an output node, said first transistor comprising a plurality of component FET devices connected in parallel, each said component device having a gate of minimum width; a second enhancement mode FET device in said substrate having its drain connected to said first node, its source connected through a diffused resistor to ground, and its gate connected to said drain potential; said second FET transistor having a gate region with a minimum length; a third enhancement mode FET transistor having its drain connected to said output node, and its gate connected to said first node; said third transistor operating as an inverting amplifier between said first node, and said output node, requiring no reference potential; a fourth enchancement mode FET transistor having its drain connected to the source of said third transistor, its source connected to ground, and its gate connected to said drain potential; a precision resistor connected between said output node and a relatively high potential; whereby a load gate voltage is generated at said output node of said circuit having a magnitude responsive to variations in the processing parameters of said integrated circuit.
Claim 2
Dependent Claim
228 words
In an integrated circuit on a semiconductor substrate, a load gate compensator circuit comprising: a first enhancement mode FET transistor in said substrate having its drain connected to a drain potential, its source connected to a first node, and its gate connected to an output node, said first transistor comprising a plurality of component FET devices connected in parallel, each said component device having a gate of minimum width; a second enhancement mode FET device in said substrate having its drain connected to said first node, its source connected through a diffused resistor to ground, and its gate connected to said drain potential; said second FET transistor having a gate region with a minimum length; a third enhancement mode FET transistor having its drain connected to said output node, and its gate connected to said first node; said third transistor operating as an inverting amplifier between said first node, and said output node, requiring no reference potential; a fourth enchancement mode FET transistor having its drain connected to the source of said third transistor, its source connected to ground, and its gate connected to said drain potential; a precision resistor connected between said output node and a relatively high potential; whereby a load gate voltage is generated at said output node of said circuit having a magnitude responsive to variations in the processing parameters of said integrated circuit.
Claim 3
Dependent Claim
34 words
The circuit of claim 1, wherein the width-to-length ratio of the gate of said first transistor is approximately three, and the width-to-length ratio of the gate region of said second transistor is approximately seven.
Claim 4
Dependent Claim
35 words
The circuit of claim 2, wherein the width-to-length ratio of the gate region of said third transistor is approximately 100 and the width-to-length ratio of the gate region of said fourth transistor is approximately five.
Claim 5
Dependent Claim
25 words
The circuit of claim 3, wherein said precision resistor has an impedance of approximately 10,000 ohms with a tolerance of plus or minus approximately 1%.
Claim 6
Dependent Claim
16 words
The circuit of claim 4, wherein said precision resistor is located outside of said semiconductor substrate.
Claim 7
Dependent Claim
27 words
The circuit of claim 1, wherein said first transistor is comprised of five component FET devices, each of which has a gate region with a minimum width.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-04-04 | 1980-10-04 | 1981-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-04-04 | 1984-10-04 | 1985-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-04-04 | 1988-10-04 | 1989-04-05 | $7700.00 | Window Closed / Lapsed |