Configuration of fuses in semiconductor structures with Cu metallization

Claim 2

A fuse configuration, comprising: a semiconductor structure having Cu metallization planes including a topmost Cu metallization plane; a diffusion barrier layer surrounding at least said topmost Cu metallization plane; an Al metal layer configured to provide Al bonding pads, said Al metal layer being provided in a topmost interconnect plane; a passivation layer covering said Al metal layer; through-contacts on said Al bonding pads extending through said diffusion barrier layer; an interconnect connected between said Al bonding pads; and wherein said interconnect is a fuse disposed above said diffusion barrier layer but below said passivation layer.

Claim 3

The configuration according to claim 1 , wherein said Al bonding pads define a metallization plane and said Al fuse is provided in said metallization plane of said Al bonding pads.

Claim 4

The configuration according to claim 1 , wherein said Al metal layer configured to provide said Al bonding pads consists of substantially only aluminum.

Claim 5

The configuration according to claim 1 , wherein said Al metal layer configured to provide said Al bonding pads is a metal sandwich layer.

Claim 6

The configuration according to claim 1 , wherein said Al metal layer includes Al interconnect and said Al fuse are part of said Al interconnects.

Claim 7

The configuration according to claim 1 , wherein said passivation layer has openings formed therein, said openings are formed above said Al fuse for keeping said Al fuse exposed.

Claim 8

The configuration according to claim 1 , wherein said topmost Cu metallization plane includes interconnects, said Al fuse are configured as bridges and electrically connect said interconnects of said topmost Cu metallization plane to one another.

Claim 9

The configuration according to claim 1 , wherein said Al fuse is configured as bridges connecting given ones of said Al bonding pads to one another.

Claim 10

A semiconductor component, comprising: a semiconductor configuration selected from the group consisting of a DRAM, a logic component and an eDRAM; and said semiconductor configuration including a fuse configuration having a semiconductor structure with Cu metallization planes including a topmost Cu metallization plane, a diffusion barrier layer surrounding at least said topmost Cu metallization plane, an Al metal layer configured to provide Al bonding pads, said Al metal layer being provided in a topmost interconnect plane, a passivation layer covering said Al metal layer, through-contacts on said bonding pads extending through said diffusion barrier layer, an interconnect connected between said bonding pads, and wherein said interconnect is a fuse disposed above said diffusion barrier layer but below said passivation layer.

Claim 11

A semiconductor component, comprising: a semiconductor configuration selected from the group consisting of a DRAM, a logic component and an eDRAM; and said semiconductor configuration including a fuse configuration having a semiconductor structure with Cu metallization planes including a topmost Cu metallization plane, a diffusion barrier layer surrounding at least said topmost Cu metallization plane, an Al metal layer configured to provide Al bonding pads, said Al metal layer being provided in a topmost interconnect plane, a passivation layer covering said Al metal layer, through-contacts on said bonding pads extending through said diffusion barrier layer, an interconnect connected between said bonding pads, and wherein said interconnect is a fuse disposed above said diffusion barrier layer but below said passivation layer.