Patent US5862373A successfully refreshed from Google Patents.
US5862373A
Expired / Lapsed
US
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Pad cells for a 2/N mode clocking scheme
Assignee: Intel Corp
•
Filing: 1996-09-06
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Granted: 1999-01-19
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Expires: 2016-09-06
Abstract
Abstract A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
Inventors
- 👤 Chakrapani Pathikonda
- 👤 Jeff Wight
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 11:54
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
150 words
An integrated circuit for use in a computer system having a bus transferring information using a bus clock signal having a frequency, said integrated circuit comprising: a plurality of pins; a core operable in response to a core clock signal that is a N/2 times the frequency of the bus clock signal, wherein every other phase of the bus clock signal is out of phase with the core clock signal; a plurality of pad cells coupling the plurality of pins to the core, wherein each pad cell comprises an input path having first and second latches coupled in series from a pin to the core and an output path having third and fourth latches coupled in series from the pin to the core, wherein the third latch is clocked by the bus clock signal and the second and fourth latches are clocked by first and second core clock signals respectively.
Claim 2
Dependent Claim
150 words
An integrated circuit for use in a computer system having a bus transferring information using a bus clock signal having a frequency, said integrated circuit comprising: a plurality of pins; a core operable in response to a core clock signal that is a N/2 times the frequency of the bus clock signal, wherein every other phase of the bus clock signal is out of phase with the core clock signal; a plurality of pad cells coupling the plurality of pins to the core, wherein each pad cell comprises an input path having first and second latches coupled in series from a pin to the core and an output path having third and fourth latches coupled in series from the pin to the core, wherein the third latch is clocked by the bus clock signal and the second and fourth latches are clocked by first and second core clock signals respectively.
Claim 3
Dependent Claim
18 words
The integrated circuit defined in claim 1 wherein the first latch is clocked by the bus clock signal.
Claim 4
Dependent Claim
15 words
The integrated circuit defined in claim 1 wherein the first latch comprises a pulsed latch.
Claim 5
Dependent Claim
18 words
The integrated circuit defined in claim 3 wherein the pulsed latch is clocked by a system clock signal.
Claim 6
Dependent Claim
15 words
The integrated circuit defined in claim 1 wherein the third latch comprises a master/slave flip-flop.
Claim 7
Dependent Claim
37 words
The integrated circuit defined in claim 1 wherein the second latch latches information on a high phase of the core clock signal, and the fourth latch latches information on a low phase of the core clock signal.
Claim 8
Dependent Claim
16 words
The integrated circuit defined in claim 1 wherein N is an odd integer greater than two.
Claim 9
Dependent Claim
24 words
The integrated circuit defined in claim 1 wherein the input path further comprises a sense amp coupled between the pin and the first latch.
Claim 10
Dependent Claim
23 words
The integrated circuit defined in claim 1 wherein the input path further comprises a buffer coupled between the pin and the first latch.
Claim 11
Dependent Claim
30 words
The integrated circuit defined in claim 1 further comprising control logic to control the core clock signal to the second latch to prevent relatching of information between core clock cycles.
Claim 12
Dependent Claim
34 words
The integrated circuit defined in claim 1 wherein the second and fourth latches hold data for one half of a core clock cycle in order to transfer the data to an appropriate clock domain.
Claim 13
Dependent Claim
20 words
The integrated circuit defined in claim 1 wherein the first and second core clock signals comprise a single clock signal.
Claim 14
Dependent Claim
25 words
The integrated circuit defined in claim 1 wherein the first and second core clock signals are separately distributed to the input and output paths respectively.
Claim 15
Dependent Claim
21 words
The integrated circuit defined in claim 1 wherein the second and fourth latches remain open when N is an even integer.
Claim 16
Dependent Claim
177 words
An integrated circuit for use in a computer system having a bus transferring information using a bus clock signal having a frequency, said integrated circuit comprising: a plurality of pins; a core operable in response to a core clock signal that is a N/2 times the frequency of the bus clock signal, wherein every other phase of the bus clock signal is out of phase with the core clock signal when N is an odd integer greater than two; a plurality of pad cells means coupling the plurality of pins to the core, wherein each pad cell comprises an input path means having first and second latching means for transferring information from one of the plurality of pins to the core and an output path means having third and fourth latching means for transferring information from the core to said one of the plurality of pins, wherein the third latching means is clocked by the bus clock signal and the second latching means and the fourth latching means are clocked by first and second core clock signals.
Claim 17
Dependent Claim
177 words
An integrated circuit for use in a computer system having a bus transferring information using a bus clock signal having a frequency, said integrated circuit comprising: a plurality of pins; a core operable in response to a core clock signal that is a N/2 times the frequency of the bus clock signal, wherein every other phase of the bus clock signal is out of phase with the core clock signal when N is an odd integer greater than two; a plurality of pad cells means coupling the plurality of pins to the core, wherein each pad cell comprises an input path means having first and second latching means for transferring information from one of the plurality of pins to the core and an output path means having third and fourth latching means for transferring information from the core to said one of the plurality of pins, wherein the third latching means is clocked by the bus clock signal and the second latching means and the fourth latching means are clocked by first and second core clock signals.
Claim 18
Dependent Claim
16 words
The integrated circuit defined in claim 15 wherein the first latching means comprise a pulsed latch.
Claim 19
Dependent Claim
18 words
The integrated circuit defined in claim 16 wherein the pulsed latch is clocked by a system clock signal.
Claim 20
Dependent Claim
16 words
The integrated circuit defined in claim 15 wherein the third latching means comprises a master/slave flip-flop.
Claim 21
Dependent Claim
39 words
The integrated circuit defined in claim 15 wherein the second latching means latches information on a high phase of the core clock signal, and the fourth latching means latches information on a low phase of the core clock signal.
Claim 22
Dependent Claim
34 words
The integrated circuit defined in claim 15 wherein the second and fourth latches hold data for one half of a core clock cycle in order to transfer the data to an appropriate clock domain.
Claim 23
Dependent Claim
20 words
The integrated circuit defined in claim 15 wherein the first and second core clock signals comprise a single clock signal.
Claim 24
Dependent Claim
25 words
The integrated circuit defined in claim 15 wherein the first and second core clock signals are separately distributed to the input and output paths respectively.
Claim 25
Dependent Claim
22 words
The integrated circuit defined in claim 15 wherein the second and fourth latching means remain open when N is an even integer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-18 | 2002-07-20 | 2003-01-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-18 | 2006-07-20 | 2007-01-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-18 | 2010-07-20 | 2011-01-19 | $7700.00 | Window Closed / Lapsed |