Method and apparatus for independently stopping and restarting functional units

Claim 2

A mechanism for powering down a functional unit on an integrated circuit, wherein the functional unit is clocked by its own independent clock, said mechanism comprising: means for indicating to the functional unit whether the functional unit is required for use; and means for powering down the functional unit coupled to said means for indicating, wherein said means for powering down the functional unit comprises stop clock logic in the functional unit that powers down the functional unit transparent to and independent of any other functional units on the integrated circuit when the functional unit is not required for use, wherein the independent clock of the functional unit is stopped by the functional unit when the functional unit is not in use and automatically started by the functional unit when the functional unit is required for use.

Claim 3

The mechanism as defined in claim I wherein said means for powering down the functional unit comprises at least one signal.

Claim 4

The mechanism as defined in claim 2 wherein said at least one signal may be asserted and deasserted on a cycle-by-cycle basis.

Claim 5

The mechanism as defined in claim 1 further comprising means for enabling and disabling the means for powering down the functional unit.

Claim 6

The mechanism as defined in claim 4 wherein the means for enabling and disabling comprises at least one register bit.

Claim 7

The mechanism as defined in claim 1 wherein said means for indicating comprises means for indicating whether the functional unit is currently in use and means for indicating whether the functional unit is going to be performing its function, such that if the functional unit is not in use and is not going to be performing its function, then the functional unit is not required for use.

Claim 8

A mechanism for powering down a functional unit on an integrated circuit, wherein the functional unit is clocked by its own independent clock, said mechanism comprising: a first interface means for providing a first internal interface to detect when the functional unit is required for use; and a second interface means for providing a second internal interface between the functional unit and its independent clock to independently and automatically stop and restart the clock of the functional unit, means for indicating to the functional unit whether the functional unit is required for use; and means for powering down the functional unit coupled to said means for indicating, wherein said means for powering down the functional unit comprises stop clock logic in the functional unit that powers down the functional unit transparent to and independent of any other functional units on the integrated circuit when the functional unit is not required for use, wherein the independent clock of the functional unit is stopped by the functional unit when the functional unit is not in use and automatically started by the functional unit using the second internal interface when the functional unit is required for use.

Claim 9

A mechanism for powering down a functional unit on an integrated circuit, wherein the functional unit is clocked by its own independent clock, said mechanism comprising: a first interface means for providing a first internal interface to detect when the functional unit is required for use; and a second interface means for providing a second internal interface between the functional unit and its independent clock to independently and automatically stop and restart the clock of the functional unit, means for indicating to the functional unit whether the functional unit is required for use; and means for powering down the functional unit coupled to said means for indicating, wherein said means for powering down the functional unit comprises stop clock logic in the functional unit that powers down the functional unit transparent to and independent of any other functional units on the integrated circuit when the functional unit is not required for use, wherein the independent clock of the functional unit is stopped by the functional unit when the functional unit is not in use and automatically started by the functional unit using the second internal interface when the functional unit is required for use.

Claim 10

The mechanism as defined in claim 7 wherein said first interface means comprises at least one signal.

Claim 11

The mechanism as defined in claim 8 wherein said first interface means includes a busy signal indicating that the functional unit is not ready for use, such that the busy signal is asserted until the clock is enabled.

Claim 12

The mechanism as defined in claim 7 wherein said second interface comprises a clock enable signal.

Claim 13

A mechanism for automatically powering down at least one of a plurality of functional units on an integrated circuit wherein said at least one functional unit executes instructions of a first type and further wherein said at least one functional unit is clocked by its own independent clock, said mechanism comprising: means for detecting whether a bus cycle to said at least one functional unit has occurred, wherein means for detecting includes means for determining whether an instruction of the first type is ready to be executed by said at least one functional unit and means for indicating to said at least one functional unit the results of the determination of said means for determining; and means in the functional unit for generating a clock enable signal to enable and disable the independent clock, such that the clock is stopped when said at least one functional unit is not required for executing instructions of the first type and automatically started when said at least one functional unit is required for executing instructions of the first type.

Claim 14

A mechanism for automatically powering down at least one of a plurality of functional units on an integrated circuit wherein said at least one functional unit executes instructions of a first type and further wherein said at least one functional unit is clocked by its own independent clock, said mechanism comprising: means for detecting whether a bus cycle to said at least one functional unit has occurred, wherein means for detecting includes means for determining whether an instruction of the first type is ready to be executed by said at least one functional unit and means for indicating to said at least one functional unit the results of the determination of said means for determining; and means in the functional unit for generating a clock enable signal to enable and disable the independent clock, such that the clock is stopped when said at least one functional unit is not required for executing instructions of the first type and automatically started when said at least one functional unit is required for executing instructions of the first type.

Claim 15

The mechanism as defined in claim 11 wherein the functional unit comprises a floating point unit and the instructions of the first type comprises floating point instructions.

Claim 16

The mechanism as defined in claim 11 wherein the means for determining comprises an instruction decoder and a microcode functional unit.

Claim 17

The mechanism as defined in claim 13 further comprising means to indicate to the decoder and microcode functional unit that said at least one functional unit is not ready to execute another instruction, wherein the mechanism indicates to the clock enable signal to enable the clock, such that when the clock is restarted the instruction decoder and microcode functional unit may continue.

Claim 18

The mechanism as defined in claim 14 wherein said means to indicate comprises a busy signal.

Claim 21

An integrated circuit for use in a computer system, said integrated circuit comprising: a plurality of functional units, wherein the plurality of functional units performs operations in the integrated circuit; and a clock generator coupled to provide clock signals to the plurality of functional units, wherein the clock generator provides a clock signal to one of the plurality of functional units, wherein said one of the plurality of functional units includes stop clock logic that determines when said one of the plurality of functional units is required for use, and wherein the stop clock logic places a first signal coupled to the clock generator in a first logic state to enable the clock signal to said one of the plurality of functional units when said one of the plurality of functional units is required for use and places the first signal in a second logic state to disable the clock signal to said one of the plurality of functional units when said one of the plurality of functional units not required for use, such that the clock signal is enabled and disabled to said one of the plurality of functional units transparently to functional units other than said one of the plurality of functional units.

Claim 22

An integrated circuit for use in a computer system, said integrated circuit comprising: a plurality of functional units, wherein the plurality of functional units performs operations in the integrated circuit; and a clock generator coupled to provide clock signals to the plurality of functional units, wherein the clock generator provides a clock signal to one of the plurality of functional units, wherein said one of the plurality of functional units includes stop clock logic that determines when said one of the plurality of functional units is required for use, and wherein the stop clock logic places a first signal coupled to the clock generator in a first logic state to enable the clock signal to said one of the plurality of functional units when said one of the plurality of functional units is required for use and places the first signal in a second logic state to disable the clock signal to said one of the plurality of functional units when said one of the plurality of functional units not required for use, such that the clock signal is enabled and disabled to said one of the plurality of functional units transparently to functional units other than said one of the plurality of functional units.

Claim 23

The integrated circuit defined in claim 17 wherein said one of the plurality of functional units is required for use when currently performing an operation or when being prepared for use.

Claim 24

The integrated circuit defined in claim 17 wherein said one of the plurality of functional units determines it is required for use in response to at least one signal generated externally to and received by said one of the plurality of functional units.

Claim 25

The integrated circuit defined in claim 19 wherein said at least one signal is generated in response to a bus cycle requesting use of said one of the plurality of functional units.

Claim 26

The integrated circuit defined in claim 19 wherein said at least one signal comprises an indication of the beginning and ending of an instruction.

Claim 27

The integrated circuit defined in claim 19 wherein the stop clock logic generates a second signal when disabling the clock signal to indicate said one of the plurality of functional units is not accepting new bus cycles.

Claim 28

The integrated circuit defined in claim 19 wherein the stop clock logic places the first signal in the first state to enable the clock signal in response to a new bus cycle after the clock signal has been disabled, wherein said one of the plurality of functional units maintains the second signal, such that one of the plurality of functional units does not accept the new bus cycle until enabling the clocks, at which time the second signal is de-asserted.

Claim 29

A processor for use in a computer system, said processor comprising: a functional unit, wherein the functional unit performs a plurality of operations to provide at least one specific function; and a clock generator coupled to the functional unit, wherein the clock generator provides a clock signal to the functional unit, wherein the functional unit comprises a first logic circuit to perform idle detection internally and a second logic circuit responsive to the first logic circuit to provide an interface of at least one signal to the clock generator to enable said clock signal to the functional unit when the first logic circuit determines that the use of the functional unit is imminent or the functional unit is performing said at least one specific function, and disable said clock signal when use of the functional unit is not imminent and the functional unit is not performing said at least one specific function, such that the functional unit internally controls enabling and disabling the clock signal.

Claim 30

A processor for use in a computer system, said processor comprising: a functional unit, wherein the functional unit performs a plurality of operations to provide at least one specific function; and a clock generator coupled to the functional unit, wherein the clock generator provides a clock signal to the functional unit, wherein the functional unit comprises a first logic circuit to perform idle detection internally and a second logic circuit responsive to the first logic circuit to provide an interface of at least one signal to the clock generator to enable said clock signal to the functional unit when the first logic circuit determines that the use of the functional unit is imminent or the functional unit is performing said at least one specific function, and disable said clock signal when use of the functional unit is not imminent and the functional unit is not performing said at least one specific function, such that the functional unit internally controls enabling and disabling the clock signal.

Claim 31

The processor defined in claim 24 wherein the first logic circuit includes circuitry to detect when a new bus cycle to the functional unit requests its use and when the new bus cycle has occurred, such that the first logic circuit determines use of the functional unit is imminent.

Claim 32

The processor defined in claim 24 further comprising a microcode unit coupled to the functional unit to indicate when a new bus cycle request for the functional unit has occurred, such that the first logic circuit determines use of the functional unit is imminent.

Claim 33

The processor defined in claim 24 further comprising a microcode unit coupled to the functional unit to indicate the beginning and ending of an instruction designated for the functional unit, wherein the first logic circuit determines the functional unit is not required for use when the instruction has ended and a new instruction is not prepared for execution, such that the second logic circuit disables the clock signal once the instruction has completed execution.

Claim 34

The processor defined in claim 24 wherein the functional unit asserts a busy signal to provide an indication external to the functional unit when the clock signal is disabled.

Claim 35

The processor defined in claim 28 wherein the functional unit enables the clock signal while asserting the busy signal, and then de-asserts the busy signal after the clock signal is enabled to the functional unit.

Claim 36

The processor defined in claim 24 wherein the second logic circuit enables and disables the clock signal on a cycle-by-cycle basis.

Claim 37

The processor defined in claim 24 further comprising an entry point programmable logic array (PLA), wherein the PLA outputs an indication signal in response to an instruction designated for the functional unit, and further wherein the second logic circuit enables the clock signal to the functional unit in response to the indication signal from the PLA.

Claim 38

The processor defined in claim 31 wherein the second logic circuit enables the clock to the functional unit at the same time the instruction arrives at the functional unit.