Programmable clock circuit

Claim 2

A programmable circuit for generating lower frequency clock signals from a higher first frequency clock signal, said circuit comprising: a first logic gate having a data input and clock input, the gate generating an output corresponding to the input on a first edge of the clock input signal, said first frequency clock signal input to the clock input of the first logic gate; a first inverter coupled to receive as input an output of the first logic gate and generating a first inverted output; a second inverter which receives as data input the first inverted output of the first inverter and generates a second inverted output; a second logic gate having a data input and ock input, the gate generating an output corresponding to the input on a first edge of the clock input signal, said second logic gate receiving as data input the second inverted output of the second inverter, said first frequency clock signal input to the clock input; a third inverter coupled to receive the output of the second logic gate and generates a third inverted output; a logical AND gate to logically AND the first inverted output of the first inverter and the third inverted output of the third inverter; a first switch coupled to receive the first inverted output of the first inverter, said first switch, when in an enabled state, generating as output a second frequency clock signal slower than the first frequency clock signal; a second switch coupled to receive the output of the logical AND gate, said second switch, when in an enabled state, generating as output a third frequency clock signal slower than the first frequency clock signal.

Claim 3

The programmable circuit as set forth in claim 1, further comprising clock pulse generating means for generating output clock pulses comprising a logical combination means for combining an enabled clock frequency signal output by an enabled switch and a corresponding phase of the first frequency clock signal such that clock pulses of the first frequency clock signal are output when the enabled clock frequency signal is in a predetermined state, and clock pulses are generated at the enabled clock frequency.

Claim 4

The programmable circuit as set forth in clclaim 2, wherein clock pulses of the first frequency clock signal are output when the enabled clock frequency signal is in a high state.

Claim 5

The programmable circuit as set forth in claim 1, wherein the frequency of the second frequency clock signal corresponds to approximately one half of the frequency of the first frequency clock signal.

Claim 6

The programmable circuit as set forth in claim 1, wherein the frequency of the third frequency clock signal corresponds to approximately one third of the frequency of the first frequency clock signal.

Claim 7

The programmable circuit as set forth in claim 1, further comprising at least one additional logic gate coupled to the circuit to enable the generation of at least one additional output clock frequency signal at a lower frequency than the frequency of the first frequency clock signal.

Claim 8

The programmable circuit as set forth in claim 1, wherein clock signals comprise a first phase clock signal and a second phase clock signal, said second phase clock signal generated in accordance with a second edge of the clock input signal.

Claim 9

The programmable circuit as set forth in claim 7, wherein the second phase clock signal of the second clock frequency signal and third clock frequency signal are generated by a second output of the first logic gate which outputs the data input signal on the second edge of the clock input.

Claim 10

The programmable circuit as set forth in claim 8, wherein the first edge is the falling edge and the second edge is the rising edge of the clock input signal.

Claim 11

The programmable circuit as set forth in claim 1, further comprising a controller for selectively enabling the first and second switches.

Claim 12

The programmable circuit as set forth in claim 10, wherein said controller further comprises means to output said first frequency clock signal.

Claim 13

A programmable circuit for generating lower clock frequencies from a higher first clock frequency, said circuit comprising: a first gate means having a data input and clock input, the gate means generating an output corresponding to the input on an edge of a clock input signal, said first frequency clock signal input to the clock input of the first gate means; a first inverter means coupled to receive as input an output of the first gate means and generating a first inverted output; a second inverter means coupled to receive as data input the first inverted output of the first inverter means and generates a second inverted output; a second gate means having a data input and clock input, the gate means generating an output corresponding to the input on an edge of the clock input, said second gate means receiving as data input the second inverted output of the second inverter means, said first clock frequency input to the clock input; a third inverter means coupled to receive the output of the second gate means and generates a third inverted output; ANDing means to logically AND the first inverted output of the first inverter and the third inverted output of the third inverter means; a first switch means coupled to receive the first inverted output of the first inverter means, said first switch, when in an enabled state, generating as output a second frequency clock signal slower than the first frequency clock signal; a second switch means coupled to receive the output of the ANDing means, said second switch, when in an enabled state, generating as output a third frequency clock signal slower than the first frequency clock signal.

Claim 14

A programmable circuit for generating lower clock frequencies from a higher first clock frequency, said circuit comprising: a first gate means having a data input and clock input, the gate means generating an output corresponding to the input on an edge of a clock input signal, said first frequency clock signal input to the clock input of the first gate means; a first inverter means coupled to receive as input an output of the first gate means and generating a first inverted output; a second inverter means coupled to receive as data input the first inverted output of the first inverter means and generates a second inverted output; a second gate means having a data input and clock input, the gate means generating an output corresponding to the input on an edge of the clock input, said second gate means receiving as data input the second inverted output of the second inverter means, said first clock frequency input to the clock input; a third inverter means coupled to receive the output of the second gate means and generates a third inverted output; ANDing means to logically AND the first inverted output of the first inverter and the third inverted output of the third inverter means; a first switch means coupled to receive the first inverted output of the first inverter means, said first switch, when in an enabled state, generating as output a second frequency clock signal slower than the first frequency clock signal; a second switch means coupled to receive the output of the ANDing means, said second switch, when in an enabled state, generating as output a third frequency clock signal slower than the first frequency clock signal.

Claim 15

The programmable circuit as set forth in claim 12, further comprising clock pulse generating means for generating output clock pulses comprising a logical combination means for combining an enabled clock frequency signal output by an enabled switch means and a corresponding phase of the first frequency clock signal such that clock pulses of the first frequency clock signal are output when the enabled clock frequency signal is in a predetermined state, and clock pulses are generated at the enabled clock frequency.

Claim 16

The programmable circuit as set forth in claim 13, wherein clock pulses of the first frequency clock signal are output when the enabled clock frequency signal is in a high state.

Claim 17

The programmable circuit as set forth in claim 12, wherein the frequency of the second frequency clock signal corresponds to approximately one half of the frequency of the first frequency clock signal.

Claim 18

The programmable circuit as set forth in claim 12, wherein the frequency of the third frequency clock signal corresponds to approximately one third of the frequency of the first frequency clock signal.

Claim 19

The programmable circuit as set forth in claim 12, further comprising at least one additional gate means coupled to the circuit to enable the generation of at least one additional output clock frequency signal at a lower frequency than the frequency of the first frequency clock signal.

Claim 20

The programmable circuit as set forth in claim 12, wherein clock signals comprise a first phase clock signal and a second phase clock signal, said second phase clock signal generated in accordance with a second edge of the clock input signal.

Claim 21

The programmable circuit as set forth in claim 18, wherein the second phase clock signal of the second clock frequency signal and third clock frequency signal are generated by a second output of the first gate means which outputs the data input signal on the second edge of the clock input signal.

Claim 22

The programmable circuit as set forth in claim 19, wherein the first edge is the falling edge and the second edge is the rising edge of the clock input signal.

Claim 23

The programmable circuit as set forth in claim 12, further comprising a control means for selectively enabling the first switch means and second switch means.

Claim 24

The programmable circuit as set forth in claim 21, wherein said control means further comprises means to output said first frequency clock signal.

Claim 25

A processing system comprising: a processor driven by a processor clock signal operating at a processor clock frequency; at least one component coupled to the processor; an input clock means for providing an input clock signal to the processing system; a processor clock means for generating the processor clock signal from the input clock signal; a clock circuit coupled to the processor clock means for generating lower frequency clock signals from the processor clock signal, said lower frequency clock signals utilized by the processor to communicate with the component, which operates at a clock frequency lower than the frequency of the processor clock signal, said clock circuit comprising; a first gate means having a clock input coupled to receive the processor clock signal and a data input, the gate means generating an output corresponding to the input on an edge of the processor clock signal, a first inverter means coupled to receive as input an output of the first gate means and generating a first inverted output; a second inverter means which receives as data input the first inverted output of the first inverter means and generates a second inverted output; a second gate means having a clock input coupled to receive the processor clock signal and a data input, the second gate means generating an output corresponding to the input on an edge of the processor clock signal, said second gate means receiving as data input the second inverted output of the second inverter means, said first frequency clock signal input to the clock input; a third inverter means coupled to receive the output of the second gate means and generates a third inverted output; ANDing means to logically AND the first inverted output of the first inverter and the third inverted output of the third inverter means; a first switch means coupled to receive the first inverted output of the first inverter means, said first switch, when in an enabled state, generating as output a second frequency clock signal slower than the first frequency clock signal; a second switch means coupled to receive the output of the ANDing means, said second switch, when in an enabled state, generating as output a third frequency clock signal slower than the first frequency clock signal.

Claim 26

A processing system comprising: a processor driven by a processor clock signal operating at a processor clock frequency; at least one component coupled to the processor; an input clock means for providing an input clock signal to the processing system; a processor clock means for generating the processor clock signal from the input clock signal; a clock circuit coupled to the processor clock means for generating lower frequency clock signals from the processor clock signal, said lower frequency clock signals utilized by the processor to communicate with the component, which operates at a clock frequency lower than the frequency of the processor clock signal, said clock circuit comprising; a first gate means having a clock input coupled to receive the processor clock signal and a data input, the gate means generating an output corresponding to the input on an edge of the processor clock signal, a first inverter means coupled to receive as input an output of the first gate means and generating a first inverted output; a second inverter means which receives as data input the first inverted output of the first inverter means and generates a second inverted output; a second gate means having a clock input coupled to receive the processor clock signal and a data input, the second gate means generating an output corresponding to the input on an edge of the processor clock signal, said second gate means receiving as data input the second inverted output of the second inverter means, said first frequency clock signal input to the clock input; a third inverter means coupled to receive the output of the second gate means and generates a third inverted output; ANDing means to logically AND the first inverted output of the first inverter and the third inverted output of the third inverter means; a first switch means coupled to receive the first inverted output of the first inverter means, said first switch, when in an enabled state, generating as output a second frequency clock signal slower than the first frequency clock signal; a second switch means coupled to receive the output of the ANDing means, said second switch, when in an enabled state, generating as output a third frequency clock signal slower than the first frequency clock signal.

Claim 27

The processing system as set forth in claim 23, wherein the component comprises memory.

Claim 28

The processing system as set forth in claim 23, wherein the at least one component and processor is coupled by a bus operating at the component clock frequency.

Claim 29

The processing system as set forth in claim 23, wherein said input clock means generates an input clock signal at a frequency different from the processor clock frequency.

Claim 30

The processing system as set forth in claim 23, wherein the processor clock means comprises a multiplier circuit to generate the processor clock signal.

Claim 31

The processing system as set forth in claim 23, wherein the input clock means is external to the processor.

Claim 32

The processing system as set forth in claim 23, wherein said clock circuit further comprising clock pulse generating means for generating output clock pulses comprising a logical combination means for combining the enabled clock frequency signal and a corresponding phase of the first clock frequency signal such that clock pulses of the first frequency clock signal are output when the enabled clock frequency signal is in a predetermined state, and clock pulses are generated at the enabled clock frequency.

Claim 33

The processing system as set forth in claim 29, wherein clock pulses of the first frequency clock signal are output when the enabled clock frequency signal is in a high state.

Claim 34

The processing system as set forth in claim 23, wherein the frequency of the second frequency clock corresponds to approximately one half of the frequency of the first frequency clock.

Claim 35

The processing system as set forth in claim 23, wherein the frequency of the third frequency clock signal corresponds to approximately one third of the frequency of the first frequency clock signal.

Claim 36

The processing system as set forth in claim 23, wherein the clock circuit further comprises at least one additional gate means to enable the generation of at least one additional output clock frequency signal at a lower frequency than the frequency of the first frequency clock signal.

Claim 37

The processing system as set forth in claim 23, wherein said control means further comprises means to output said first frequency clock signal.

Claim 38

The processing system as set forth in claim 23, wherein clock signals comprise a first phase clock signal and a second phase clock signal, said second phase clock signal generated in accordance with a second edge of the clock input signal.

Claim 39

The processing system as set forth in claim 35, wherein the second phase clock signal of the second clock frequency signal and third clock frequency signal are generated by a second output of the first gate means which outputs the data input signal on the second edge of the clock input signal.

Claim 40

The processing system as set forth in claim 36, wherein the first edge is the falling edge and the second edge is the rising edge of the clock input signal.

Claim 43

The method as set forth in claim 38, further comprising the step of selecting an output signal from the first lower frequency clock signal and the second lower frequency clock signal.

Claim 44

The method as set forth in claim 39, wherein said step of selecting comprises the step of controlling switches which selectively couple the first and second lower frequency clock signal as the output clock signal.

Claim 45

The method as set forth in claim 38, further comprising the step of selecting an output clock signal from the higher first frequency clock signal the first lower frequency clock signal and the second lower frequency clock signal.

Claim 46

The method as set forth in claim 38, further comprising the step of generating output clock pulses by logically combining the enabled clock frequency signal and a corresponding first clock frequency signal such that clock pulses of the first clock frequency signal are output when the enabled clock frequency signal is in a predetermined state, and clock pulses are generated at the enabled clock frequency.

Claim 47

The method as set forth in claim 38, wherein the first lower clock frequency corresponds to approximately one half of the first clock frequency.

Claim 48

The method as set forth in claim 38, wherein the second lower clock frequency corresponds to approximately one third of the first clock frequency.

Claim 49

The method as set forth in claim 38, further comprising the steps of generating additional lower frequency clock signals by generating additional output signals and logically combining the output signals to generate the additional lower frequency clock signals.

Claim 50

The method as set forth in claim 38, wherein clock signals comprise a first phase clock signal and a second phase clock signal, and the second phase clock signal of the second clock frequency signal and third clock frequency signal are generated by gating a first data input signal according to a second edge of the first frequency clock signal.

Claim 51

The method as set forth in claim 46, wherein the first edge is the falling edge and the second edge is the rising edge of the first frequency clock signal.