Variable-ratio frequency divider

Claim 2

A variable-ratio frequency divider comprising delay means providing a signal delay time which can be set according to a desired frequency-dividing ratio; a first D flip-flop having a feedback loop including said delay means connected from one output terminal to a set input terminal thereof and with the data input terminal thereof maintained at a logic low level; a second D flip-flop having a data input terminal connected to the other output terminal of said first D flip-flop and having the clock terminal thereof connected to receive a basic clock signal to be frequency-divided; and a delay element connected between the clock input of said first D flip-flop and one output terminal of said second D flip-flop, the other output terminal of said second D flip-flop providing a frequency-divided clock signal output.

Claim 3

A variable-ratio frequency divider comprising delay means providing a signal delay time which can be set according to a desired frequency-dividing ratio; a first D flip-flop having a feedback loop including said delay means connected from one output terminal thereof to the set terminal thereof and with the reset terminal thereof maintained at a logic high level; a second D flip-flop having a data input terminal connected to the other output terminal of said first D flip-flop and having the clock terminal thereof connected to receive a basic clock signal to be frequency-divided; and a delay element providing an output delayed by a predetermined value and connected between the clock input to said first D flip-flop and one output terminal of said second D flip-flop, the other output terminal of said second D flip-flop providing a frequency-divided clock signal output.

Claim 4

A variable-ratio frequency divider comprising delay means providing a signal delay time which can be set according to a desired frequency-dividing ratio; a first D flip-flop having a feedback loop including said delay means connected from one output terminal thereof to the set terminal thereof and with the reset terminal thereof maintained at a logic high level; a second D flip-flop having a data input terminal connected to the other output terminal of said first D flip-flop and having the clock terminal thereof connected to receive a basic clock signal to be frequency-divided; and a delay element providing an output delayed by a predetermined value and connected between the clock input to said first D flip-flop and one output terminal of said second D flip-flop, the other output terminal of said second D flip-flop providing a frequency-divided clock signal output.

Claim 5

A variable-ratio frequency divider circuit comprising delay means providing a signal delay time which can be set according to a desired frequency-dividing ratio; a first D flip-flop having at least a pair of feedback loops connected from the inverted output terminal thereof to the clock terminal thereof and with the data input terminal thereof maintained at a logic low level, one of said feedback loops including said delay means; a second D flip-flop having the other output terminal of said first D flip-flop connected to the data input terminal thereof and with the clock terminal thereof connected to receive a basic clock signal to be frequency-divided; a delay element connected between one output of said second D flip-flop and a set input to said first D flip-flop; and control means including a counter and connected between said inverted output terminal of said first D flip-flop and said pair of feedback loops for switching said feedback loops, whereby said one of said feedback loops produces a frequency-divided clock signal.

Claim 6

A variable-ratio frequency divider circuit comprising delay means providing a signal delay time which can be set according to a desired frequency-dividing ratio; a first D flip-flop having at least a pair of feedback loops connected from the inverted output terminal thereof to the clock terminal thereof and with the data input terminal thereof maintained at a logic low level, one of said feedback loops including said delay means; a second D flip-flop having the other output terminal of said first D flip-flop connected to the data input terminal thereof and with the clock terminal thereof connected to receive a basic clock signal to be frequency-divided; a delay element connected between one output of said second D flip-flop and a set input to said first D flip-flop; and control means including a counter and connected between said inverted output terminal of said first D flip-flop and said pair of feedback loops for switching said feedback loops, whereby said one of said feedback loops produces a frequency-divided clock signal.