US4041403A
Expired / Lapsed
US
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Divide-by-N/2 frequency division arrangement
Assignee: AT&T Inc
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Filing: 1975-07-28
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Granted: 1977-08-09
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Expires: 1995-07-28
Abstract
Abstract An arrangement for frequency division of a symmetrical pulse train by N/2 where N is an odd integer greater than 1; this arrangement does not require the use of any one-shot multivibrators or delay elements and employs only log 2 (N+1) flip-flops in its design. In one embodiment a two state gating circuit selectively allows either the input pulse train or its inverse to be fed to a modulo (N+1)/2 counter. The state of the gating circuit is controlled by a flip-flop which toggles whenever the counter reaches its maximum count. In addition, the counter produces an output pulse as it advances through each of its counting sequences. Thus, the counter, which advances in response to falling pulse edges, alternates between counting falling edges of the input pulse train and the inverted input pulse train thereby counting to N+1 in N pulse periods while yielding two equally-spaced output pulses.
Inventors
- 👤 Richard Samuel Chiapparoli, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 01:33
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/64; H03K23/66; H03K23/662
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
310 words
A frequency divider circuit for deriving two output pulses for every N input pulses where N is an odd number comprising: a source of pulses, gating means having two operating states and a pair of inputs selectively actuatable to switch from either of said states to the other thereof, a third input connected to said source and an output terminal for reproducing said input pulses at said output terminal in one of said states and for inverting said input pulses at said output terminal in the other of said states, synchronous counter means having an input connected to said gating means output terminal and selectively operated in response to a receipt of each group of (N+1)/2 of said reproduced and of said inverted input pulses from said output terminal for producing an output pulse, said counter means including, a plurality of J-K flip-flops each having a J data input, a K data input, a clock input and logic outputs, means for interconnecting particular ones of said data inputs and said outputs of said plurality of flip-flops, and means connecting said clock inputs of each of said flip-flops in parallel to said gating means output terminal for changing the state of individual ones of said flip-flops in response to a receipt of a pulse from said gating means output terminal synchronously to increment a pulse count, and toggle switch means having outputs connected selectively to actuate one of said pair of inputs of said gating means and an input responsive to a receipt of said counter means output pulse for effecting a toggling of said switch means to switch the state of said gating means and for effecting the inverting of said pulses at said gating means output terminal to yield two equally spaced output pulses upon the receipt of two of said groups of (N+1)/2 pulses at said output terminal.
Claim 2
Dependent Claim
310 words
A frequency divider circuit for deriving two output pulses for every N input pulses where N is an odd number comprising: a source of pulses, gating means having two operating states and a pair of inputs selectively actuatable to switch from either of said states to the other thereof, a third input connected to said source and an output terminal for reproducing said input pulses at said output terminal in one of said states and for inverting said input pulses at said output terminal in the other of said states, synchronous counter means having an input connected to said gating means output terminal and selectively operated in response to a receipt of each group of (N+1)/2 of said reproduced and of said inverted input pulses from said output terminal for producing an output pulse, said counter means including, a plurality of J-K flip-flops each having a J data input, a K data input, a clock input and logic outputs, means for interconnecting particular ones of said data inputs and said outputs of said plurality of flip-flops, and means connecting said clock inputs of each of said flip-flops in parallel to said gating means output terminal for changing the state of individual ones of said flip-flops in response to a receipt of a pulse from said gating means output terminal synchronously to increment a pulse count, and toggle switch means having outputs connected selectively to actuate one of said pair of inputs of said gating means and an input responsive to a receipt of said counter means output pulse for effecting a toggling of said switch means to switch the state of said gating means and for effecting the inverting of said pulses at said gating means output terminal to yield two equally spaced output pulses upon the receipt of two of said groups of (N+1)/2 pulses at said output terminal.
Claim 3
Dependent Claim
182 words
The arrangement in accordance with claim 1 wherein N has a value of 5, said plurality of J-K flip-flops includes a first and a second J-K flip-flop, each said logic outputs has a logic zero and a logic one output and said interconnecting means comprises a first connection between said J data input of said first flip-flop and said zero output of said second flip-flop, a second connection between said logic one output of said first flip-flop and said J input of said second flip-flop, a third connection between said K input of said first flip-flop and a logic one voltage source, a fourth connection between said K input of said second flip-flop and said logic one voltage source, a first counter output lead connected to said logic one output of said second flip-flop to provide two equally-spaced divider output pulses for every five divider input pulses, and a second output counter lead connected to said logic one output of said second flip-flop to provide said counter means output pulse to toggle said toggle switch means after every three counter input pulses.
Claim 4
Dependent Claim
284 words
An arrangement for dividing the frequency of symmetrical input pulses by N/2 where N is an odd number comprising: logic circuit means having a first input to receive said symmetrical input pulses and a pair of control terminals for determining the passage to an output terminal of an exact replica of said input pulses when operating a first mode and the passage of an inverted replica thereof when operating in a second mode, bistable switch means having a pair of outputs connected to said pair of control terminals for switching the operating mode of said logic circuit means, counting means connected to said output terminal of said logic circuit means and resettable in response to a receipt of a sequence of (N+1)/2 of said inverted replica or of said exact replica of said input pulses for producing an output pulse during said sequence, wherein said counting means includes: a plurality of interconnected flip-flops each having a logic output actuated to a predetermined logic value when a pulse is received at a clock input thereof, and decoder gating means having inputs connected to any said logic output of particular ones of said flip-flops for selectively deriving said output pulse upon a receipt of any designated one of said (N+1)/2 pulses of said sequence to allow the production of said output pulse during the achievement of any preselected one of a plurality of counts by said counting means, and means connected between said counting means and said switch means operated in response to a receipt by said counting means of the last pulse in said sequence for activating said switch means to switch the mode of said logic circuit means at the end of said sequence.
Claim 5
Dependent Claim
284 words
An arrangement for dividing the frequency of symmetrical input pulses by N/2 where N is an odd number comprising: logic circuit means having a first input to receive said symmetrical input pulses and a pair of control terminals for determining the passage to an output terminal of an exact replica of said input pulses when operating a first mode and the passage of an inverted replica thereof when operating in a second mode, bistable switch means having a pair of outputs connected to said pair of control terminals for switching the operating mode of said logic circuit means, counting means connected to said output terminal of said logic circuit means and resettable in response to a receipt of a sequence of (N+1)/2 of said inverted replica or of said exact replica of said input pulses for producing an output pulse during said sequence, wherein said counting means includes: a plurality of interconnected flip-flops each having a logic output actuated to a predetermined logic value when a pulse is received at a clock input thereof, and decoder gating means having inputs connected to any said logic output of particular ones of said flip-flops for selectively deriving said output pulse upon a receipt of any designated one of said (N+1)/2 pulses of said sequence to allow the production of said output pulse during the achievement of any preselected one of a plurality of counts by said counting means, and means connected between said counting means and said switch means operated in response to a receipt by said counting means of the last pulse in said sequence for activating said switch means to switch the mode of said logic circuit means at the end of said sequence.
References Cited (Backward Citations)
US3189832A
Cited
US3446947A
Cited
US3430067A
Cited
US3571728A
Cited
US3818354A
Cited
US3896387A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-08 | 1981-02-07 | 1981-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-08 | 1985-02-07 | 1985-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-08 | 1989-02-07 | 1989-08-09 | $7700.00 | Window Closed / Lapsed |