Frequency divider

Abstract

Abstract PURPOSE:To obtain a frequency divider using a high speed clock so as to attain optional frequency division by utilizing an M series generator as a counter. CONSTITUTION:The M series generator consists of AND circuits 1-5, DFF 2-4 and an EXNOR circuit 9. The M series generator is reset and generates an M series at the leading of a clock after the terminal Q of each DFF goes to L. When the output of a NAND circuit 10 goes to L by the output of each DFF, the terminal Q of all the DFFs goes again to L at the next clock. Thus, a part of the output of the NAND circuit 10, corresponding to the period by one clock only among clock numbers required for the terminals Q of all the DFFs going to L level goes to N L level, then a frequency division output is obtained. 2-(2N-1) ways of optional frequency division are applied by the combination of inputs to the NAND circuit. Thus, the frequency divider applying optional frequency division while using a high speed clock is obtained.

Inventors

• 👤 Kenji Muraki
• 👤 健司 村木
• 👤 Mikio Oda
• 👤 幹夫 小田

Bibliographic Details