Patent US5084976A successfully refreshed from Google Patents.
US4646331A
Expired / Lapsed
US
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Electronic static switched-latch frequency divider circuit with odd number counting capability
Assignee: Intersil Corp
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Filing: 1985-04-01
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Granted: 1987-02-24
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Expires: 2005-04-01
Abstract
Abstract An electronic frequency divider circuit, particularly well-adapted to implement odd-number counters, comprising a multiplicity of switched-latch stages, and in the case of an odd-number counter, further including a bypass circuit stage. Each switched-latch stage comprises a first transmission gate and two inverters configured as a latch circuit, and a second transmission gate for coupling the latch circuit to a previous stage. Even-number divider circuits may be implemented using only pairs of switched-latch stages without the bypass circuit.
Inventors
- 👤 Glenn L. Ely
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:57
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/40; H03K23/48; H03K23/483; H03K23/42; H03K23/44
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
344 words
An electronic static switched-latch odd frequency divider circuit comprising: (a) a first stage comprising a first transmission gate coupled to and controlled by a clock signal, said first transmission gate having an input and an output and transmitting signals therethrough when said clock signal has a first level, and a first switched-latch means coupled to the output of the first transmission gate, the input of said first transmission gate providing the input of said first stage and the output of said first switched latch means providing the output of said first stage; (b) a second stage comprising a second transmission gate coupled to and controlled by said clock signal, said second transmission gate having an input and an output and transmitting signals therethrough when said clock signal has a second level, and a second switched-latch means coupled to the output of the second transmission gate, the input of said second transmission gate providing the input of said second stage and the output of said second switched-latch means providing the output of said second stage the input of the second stage being coupled to the output of the first stage; (c) bypass circuit means coupled to the output of the second stage for selectively inverting the output of the second stage in a manner which alternates between two even frequency divider modes resulting on average in the desired odd division; and (d) a third stage comprising a third transmission gate coupled to and controlled by said clock signal, said third transmission gate having an input and an output and transmitting signals therethrough when said clock signal has said second level, and a third switched-latch means coupled to the output of the third transmission gate, the input of said third transmission gate providing the input of said third stage and the output of said third switched-latch means providing the output of said third stage the input of the third stage being coupled to the output of the bypass circuit means, and the output of the third stage being coupled to the input of the first stage.
Claim 2
Dependent Claim
344 words
An electronic static switched-latch odd frequency divider circuit comprising: (a) a first stage comprising a first transmission gate coupled to and controlled by a clock signal, said first transmission gate having an input and an output and transmitting signals therethrough when said clock signal has a first level, and a first switched-latch means coupled to the output of the first transmission gate, the input of said first transmission gate providing the input of said first stage and the output of said first switched latch means providing the output of said first stage; (b) a second stage comprising a second transmission gate coupled to and controlled by said clock signal, said second transmission gate having an input and an output and transmitting signals therethrough when said clock signal has a second level, and a second switched-latch means coupled to the output of the second transmission gate, the input of said second transmission gate providing the input of said second stage and the output of said second switched-latch means providing the output of said second stage the input of the second stage being coupled to the output of the first stage; (c) bypass circuit means coupled to the output of the second stage for selectively inverting the output of the second stage in a manner which alternates between two even frequency divider modes resulting on average in the desired odd division; and (d) a third stage comprising a third transmission gate coupled to and controlled by said clock signal, said third transmission gate having an input and an output and transmitting signals therethrough when said clock signal has said second level, and a third switched-latch means coupled to the output of the third transmission gate, the input of said third transmission gate providing the input of said third stage and the output of said third switched-latch means providing the output of said third stage the input of the third stage being coupled to the output of the bypass circuit means, and the output of the third stage being coupled to the input of the first stage.
Claim 3
Dependent Claim
109 words
The divider circuit of claim 1 wherein each switched-latch means comprises: (a) a first inverter, wherein the input and output of the first inverter serves as the input and output of the switched-latch means; (b) a second inverter, the input of which is coupled to the output of the first inverter; and (c) transmission gate means, the input of which is coupled to the output of the second inverter, the output of which is coupled to the input of the first inverter, and which is coupled to and controlled by said clock signal, for selectively coupling the output of the second inverter to the input of the first inverter.
Claim 4
Dependent Claim
68 words
The odd frequency divider circuit of claim 1 further comprising at least one additional pair of stages connected between said second stage and said bypass circuit means, each of said additional pairs of stages including a stage identical to said first stage and a stage identical to said second stage, whereby division by any odd number may be obtained by adding the appropriate number of pairs of stages.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-23 | 1990-08-25 | 1991-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-23 | 1994-08-25 | 1995-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-23 | 1998-08-25 | 1999-02-24 | $7700.00 | Window Closed / Lapsed |