High speed resettable dynamic counter

Claim 2

A counter stage in combination with a source of cyclical signals having a first binary significance during a first portion of the cycle and having a second binary significance during a second portion of the cycle, comprising: a first section and a second section, one of said first and second sections having an input and an output at which is produced a signal 180° out-of-phase with a signal at its input, and the other one of said first and second sections having an input and an output at which is produced a signal in-phase with a signal at its input; a first transmission gate connected between the output of the first section and the input to the second section for, when enabled, coupling the output of the first section to the input of the second section; a second transmission gate connected between the output of the second section and the input of the first section for, when enabled, coupling the output of the second section to the input of the first section; resetting means coupled to the input of the first section for, when enabled, setting the input of the first section to a predetermined level; means for continuously applying said cyclical signals to said first and second transmission gates for enabling said first transmission gate and disabling said second transmission gate during said first portion of each cycle, and for enabling said second transmission gate and disabling said first transmission gate during said second portion of each cycle; a terminal adapted to receive a reset signal; and gating means responsive to said cyclical signals and to said reset signal for enabling said resetting means only during said first portion of each cycle and when a reset signal is present.

Claim 3

The combination as claimed in claim 1 wherein said resetting means includes a transistor having a conduction path and a control electrode and wherein its conduction path is connected between the input of said first section and a point of fixed reference potential; and wherein said gating means responsive to said clock signal and to said reset signal includes a first logic gate having at least two inputs and one output and wherein said cyclical signal is applied to one of its inputs and said reset signal is applied to another one of its inputs and wherein its output is connected to the control electrode of said transistor of said resetting means.

Claim 4

The combination as claimed in claim 2 wherein said second section includes a second logic gate having two inputs and one output, wherein one of its two inputs is connected to the input of said second section and wherein the other one of its two inputs is connected to the output of said first logic gate.

Claim 5

The combination as claimed in claim 3 wherein said second section also includes an inverting stage having an input connected to the output of said second logic gate and having an output connected to the output of said second section; and wherein said first section includes an inverting stage having an input connected to the input of said first section and its output connected to the output of said first section.

Claim 6

A high speed counter comprising: a source of cyclical input signals to be counted, said input signals having a first and a second portion per cycle; a resettable counter stage for counting said input signals and producing output signals responsive to said input signals including: (a) a master section and a slave section; (b) a first transmission gate connected between the output of the master section and the input to the slave section; (c) a second transmission gate connected between the output of the slave section and the input of the master section; and (d) means applying said input signals to said first and second transmission gates for enabling said first transmission gate and disabling said second transmission gate during said first portion and for enabling said second transmission gate and disabling said first transmission gate during said second portion of each input signal cycle; K-1 cascaded counter stages for counting, when enabled, the output signals of said resettable stage where K is an integer greater than 1; and resetting means coupled to the input of said master section responsive to a predetermined state of said K-1 counter stages and of said resettable stage, and to said input signal being in said first portion of its cycle for resetting the master section of said first stage while said second transmission gate is disabled.

Claim 7

A high speed counter comprising: a source of cyclical input signals to be counted, said input signals having a first and a second portion per cycle; a resettable counter stage for counting said input signals and producing output signals responsive to said input signals including: (a) a master section and a slave section; (b) a first transmission gate connected between the output of the master section and the input to the slave section; (c) a second transmission gate connected between the output of the slave section and the input of the master section; and (d) means applying said input signals to said first and second transmission gates for enabling said first transmission gate and disabling said second transmission gate during said first portion and for enabling said second transmission gate and disabling said first transmission gate during said second portion of each input signal cycle; K-1 cascaded counter stages for counting, when enabled, the output signals of said resettable stage where K is an integer greater than 1; and resetting means coupled to the input of said master section responsive to a predetermined state of said K-1 counter stages and of said resettable stage, and to said input signal being in said first portion of its cycle for resetting the master section of said first stage while said second transmission gate is disabled.

Claim 8

The combination as claimed in claim 5 wherein said master section has an input and an output at which is produced a signal 180° out-of-phase with the signal at its input, and wherein said slave section has an input and an output at which is produced a signal in-phase with the signal at its input.

Claim 9

The combination as claimed in claim 6 wherein said resetting means includes at least first and second transistors having their conduction paths connected in series between said input of said master section and a point of reference potential; wherein a signal is applied to the control electrode of the first transistor for turning it on only when said second transmission gate is disabled; and wherein a signal is applied to the control electrode of the second transistor for turning it on when said resettable counter stage and K-1 cascaded stages are in said predetermined state.

Claim 10

The combination as claimed in claim 7 wherein said K-1 cascaded counter stages form a count-down ripple-down binary counter; and further including means coupled to the K-1 counter stages for setting a selected count into said counter.

Claim 11

The combination as claimed in claim 8 wherein said means responsive to a predetermined state of said K-1 counter stages and said resettable counter stage includes decoding means coupled to said K-1 counter stages and to said first stage for sensing said predetermined state, and, in response thereto, producing an output signal which is selectively applied to the control electrode of the second transistor of said resetting means.

Claim 12

A high speed counter comprising: a source of cyclical input signals to be counted, said input signals having a first and a second portion per cycle; a resettable counter stage for counting said input signals and producing output signals responsive to said input signals including: (a) first and second sections, each section having an input and an output; one of said first and second sections having an output at which is produced a signal 180° out-of-phase with a signal applied to its input, and the other one of said first and second sections having an output at which is produced a signal in-phase with a signal applied to its input; and (b) means responsive to said cyclical input signals for coupling said output of said first stage to said input of said second stage and decoupling the output of said second stage from the input of said first stage during said first portion of each cycle and for coupling said output of said second stage to said input of said first stage and decoupling the output of said first stage from the input of said second stage during said second portion of each cycle; K-1 cascaded counter stages for counting, when enabled, the output signals of said resettable stage where K is an integer greater than 1; and resetting means coupled to the input of said first section, responsive to a predetermined state of said K-1 counter stages and of said resettable stage, and to said input signal being in said first portion of its cycle for resetting said first section of said first stage while said output of said second stage is decoupled from said input of said first stage and while said second section is already in the state in which it would be placed by the transfer of the output of the first section to the input of the second section.

Claim 13

A high speed counter comprising: a source of cyclical input signals to be counted, said input signals having a first and a second portion per cycle; a resettable counter stage for counting said input signals and producing output signals responsive to said input signals including: (a) first and second sections, each section having an input and an output; one of said first and second sections having an output at which is produced a signal 180° out-of-phase with a signal applied to its input, and the other one of said first and second sections having an output at which is produced a signal in-phase with a signal applied to its input; and (b) means responsive to said cyclical input signals for coupling said output of said first stage to said input of said second stage and decoupling the output of said second stage from the input of said first stage during said first portion of each cycle and for coupling said output of said second stage to said input of said first stage and decoupling the output of said first stage from the input of said second stage during said second portion of each cycle; K-1 cascaded counter stages for counting, when enabled, the output signals of said resettable stage where K is an integer greater than 1; and resetting means coupled to the input of said first section, responsive to a predetermined state of said K-1 counter stages and of said resettable stage, and to said input signal being in said first portion of its cycle for resetting said first section of said first stage while said output of said second stage is decoupled from said input of said first stage and while said second section is already in the state in which it would be placed by the transfer of the output of the first section to the input of the second section.