US3887822A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Flip-flop circuits utilizing insulated gate field effect transistors
Assignee: Toshiba Corp
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Filing: 1973-08-03
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Granted: 1975-06-03
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Expires: 1993-08-03
Abstract
Abstract A flip-flop circuit utilizing insulated gate field effect transistors or MOS transistors and operating as a set dominant type or a reset dominant type includes a delayed logic circuitry having a three-input logic circuit comprised of an AND-NOR gate constituted by P and N channel MOS transistors, and P and N channel clocked MOS transistors for operating the logic circuit in synchronism with a clock signal and a complement thereof. The output of the delayed logic circuitry is reversed in polarity by a first complementary MOS inverter. The three-input logic circuit receives a first logical input through a second complementary MOS inverter, a second logical input, and the output of the flip-flop circuit.
Inventors
- 👤 Yasoji Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:40
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
454 words
A flip-flop circuit utilizing insulated gate field effect transistors, comprising: a source of first and second logical inputs; a source of operating voltage; a source of first complementary clock signals; first inverter means including a complementary pair of field effect transistors for receiving and reversing the polarity of said first logical input; delayed logic circuit means comprising first to fourth transistors of one channel type each including source and drain regions defining therebetween a conduction path and a gate electrode, and fifth to eighth transistors of the other channel type each including source and drain regions defining therebetween a conduction path and a gate electrode, the conduction paths of said first and second transistors being coupled in parallel, the conduction path of said third transistor being connected in series with that of said first transistor, the conduction paths of said fifth and sixth transistors being connected in series, the conduction path of said seventh transistor being connected in parallel with serially connected conduction paths of said fifth and sixth transistors, the conduction path of said second transistor being connected in series with that of said seventh transistor, the conduction path of said fourth transistor being connected between the conduction path of said third transistor and one terminal of said source of operating voltage, the conduction path of said eighth transistor being connected between the conduction path of said fifth transistor and the other terminal of said source of operating voltage, the gate electrodes of said first and fifth transistors being connected in common to receive the output of said first inverter means, the gate electrodes of said second and sixth transistors being connected in common to receive an output of said flip-flop circuit, the gate electrodes of said third and seventh transistors being connected in common to receive said second logical input, the gate electrodes of said fourth and eighth transistors being connected to said clock signal source to receive respectively complementary clock signals, and the junction between the conduction paths of said second and seventh transistors comprising an output of said delayed logic circuit means; and second inverter means coupled to the output of said delayed logic circuit means, and including a complementary pair of field effect transistors for receiving and reversing the polarity of the outputs of said delayed logic circuit means to provide the output of said flip-flop circuit; whereby when the states of first and second logical inputs are in a predetermined combination, the output state of the flip-flop circuit is held, and when the states of said first and second logical inputs are in other combinations, either one of said first and second logical inputs is dominantly derived out on the output side in response to said clock signals.
Claim 2
Dependent Claim
454 words
A flip-flop circuit utilizing insulated gate field effect transistors, comprising: a source of first and second logical inputs; a source of operating voltage; a source of first complementary clock signals; first inverter means including a complementary pair of field effect transistors for receiving and reversing the polarity of said first logical input; delayed logic circuit means comprising first to fourth transistors of one channel type each including source and drain regions defining therebetween a conduction path and a gate electrode, and fifth to eighth transistors of the other channel type each including source and drain regions defining therebetween a conduction path and a gate electrode, the conduction paths of said first and second transistors being coupled in parallel, the conduction path of said third transistor being connected in series with that of said first transistor, the conduction paths of said fifth and sixth transistors being connected in series, the conduction path of said seventh transistor being connected in parallel with serially connected conduction paths of said fifth and sixth transistors, the conduction path of said second transistor being connected in series with that of said seventh transistor, the conduction path of said fourth transistor being connected between the conduction path of said third transistor and one terminal of said source of operating voltage, the conduction path of said eighth transistor being connected between the conduction path of said fifth transistor and the other terminal of said source of operating voltage, the gate electrodes of said first and fifth transistors being connected in common to receive the output of said first inverter means, the gate electrodes of said second and sixth transistors being connected in common to receive an output of said flip-flop circuit, the gate electrodes of said third and seventh transistors being connected in common to receive said second logical input, the gate electrodes of said fourth and eighth transistors being connected to said clock signal source to receive respectively complementary clock signals, and the junction between the conduction paths of said second and seventh transistors comprising an output of said delayed logic circuit means; and second inverter means coupled to the output of said delayed logic circuit means, and including a complementary pair of field effect transistors for receiving and reversing the polarity of the outputs of said delayed logic circuit means to provide the output of said flip-flop circuit; whereby when the states of first and second logical inputs are in a predetermined combination, the output state of the flip-flop circuit is held, and when the states of said first and second logical inputs are in other combinations, either one of said first and second logical inputs is dominantly derived out on the output side in response to said clock signals.
Claim 3
Dependent Claim
454 words
A flip-flop circuit utilizing insulated gate field effect transistors, comprising: a source of first and second logical inputs; a source of operating voltage; a source of first complementary clock signals; first inverter means including a complementary pair of field effect transistors for receiving and reversing the polarity of said first logical input; delayed logic circuit means comprising first to fourth transistors of one channel type each including source and drain regions defining therebetween a conduction path and a gate electrode, and fifth to eighth transistors of the other channel type each including source and drain regions defining therebetween a conduction path and a gate electrode, the conduction paths of said first and second transistors being coupled in parallel, the conduction path of said third transistor being connected in series with that of said first transistor, the conduction paths of said fifth and sixth transistors being connected in series, the conduction path of said seventh transistor being connected in parallel with serially connected conduction paths of said fifth and sixth transistors, the conduction path of said second transistor being connected in series with that of said seventh transistor, the conduction path of said fourth transistor being connected between the conduction path of said third transistor and one terminal of said source of operating voltage, the conduction path of said eighth transistor being connected between the conduction path of said fifth transistor and the other terminal of said source of operating voltage, the gate electrodes of said first and fifth transistors being connected in common to receive the output of said first inverter means, the gate electrodes of said second and sixth transistors being connected in common to receive an output of said flip-flop circuit, the gate electrodes of said third and seventh transistors being connected in common to receive said second logical input, the gate electrodes of said fourth and eighth transistors being connected to said clock signal source to receive respectively complementary clock signals, and the junction between the conduction paths of said second and seventh transistors comprising an output of said delayed logic circuit means; and second inverter means coupled to the output of said delayed logic circuit means, and including a complementary pair of field effect transistors for receiving and reversing the polarity of the outputs of said delayed logic circuit means to provide the output of said flip-flop circuit; whereby when the states of first and second logical inputs are in a predetermined combination, the output state of the flipflop circuit is held, and when the states of said first and second logical inputs are in other combinations, either one of said first and second logical inputs is dominantly derived out on the output side in response to said clock signals.
Claim 4
Dependent Claim
454 words
A flip-flop circuit utilizing insulated gate field effect transistors, comprising: a source of first and second logical inputs; a source of operating voltage; a source of first complementary clock signals; first inverter means including a complementary pair of field effect transistors for receiving and reversing the polarity of said first logical input; delayed logic circuit means comprising first to fourth transistors of one channel type each including source and drain regions defining therebetween a conduction path and a gate electrode, and fifth to eighth transistors of the other channel type each including source and drain regions defining therebetween a conduction path and a gate electrode, the conduction paths of said first and second transistors being coupled in parallel, the conduction path of said third transistor being connected in series with that of said first transistor, the conduction paths of said fifth and sixth transistors being connected in series, the conduction path of said seventh transistor being connected in parallel with serially connected conduction paths of said fifth and sixth transistors, the conduction path of said second transistor being connected in series with that of said seventh transistor, the conduction path of said fourth transistor being connected between the conduction path of said third transistor and one terminal of said source of operating voltage, the conduction path of said eighth transistor being connected between the conduction path of said fifth transistor and the other terminal of said source of operating voltage, the gate electrodes of said first and fifth transistors being connected in common to receive the output of said first inverter means, the gate electrodes of said second and sixth transistors being connected in common to receive an output of said flip-flop circuit, the gate electrodes of said third and seventh transistors being connected in common to receive said second logical input, the gate electrodes of said fourth and eighth transistors being connected to said clock signal source to receive respectively complementary clock signals, and the junction between the conduction paths of said second and seventh transistors comprising an output of said delayed logic circuit means; and second inverter means coupled to the output of said delayed logic circuit means, and including a complementary pair of field effect transistors for receiving and reversing the polarity of the outputs of said delayed logic circuit means to provide the output of said flip-flop circuit; whereby when the states of first and second logical inputs are in a predetermined combination, the output state of the flipflop circuit is held, and when the states of said first and second logical inputs are in other combinations, either one of said first and second logical inputs is dominantly derived out on the output side in response to said clock signals.
Claim 5
Dependent Claim
37 words
A flip-flop circuit according to claim 1 wherein said first to eighth transistors comprise an AND gate for receiving two inputs and a NOR gate for receiving the output of said AND gate and another one input.
Claim 6
Dependent Claim
38 words
A flip-flop circuit according to claim 1 wherein said first to eighth transistors comprise an OR gate for receiving two inputs, and a NAND gate for receiving the output of said OR gate circuit and another one input.
Claim 7
Dependent Claim
47 words
A flip-flop circuit according to claim 1 which further comprises a stabilizing circuit connected to the output of said delayed logic circuit means for holding the output voltage of said logic circuit means for a predetermined length of time after said delayed logic circuit means has operated.
Claim 8
Dependent Claim
63 words
A flip-flop circuit according to claim 4 wherein said stabilizing circuit comprises an inverter including a complementary pair of field effect transistors, and a clocked inverter having a complementaRy pair of field effect transistors, the input of said clocked inverter being connected to the output of said inverter and the output of said clocked inverter being connected to the input of said inverter.
Claim 9
Dependent Claim
41 words
A flip-flop circuit according to claim 4 wherein said stabilizing circuit comprises an inverter including a complementary pair of field effect transistors, and a clocked inverter including a complementary pair of field effect transistors and connected in cascade with said inverter.
Claim 10
Dependent Claim
66 words
A flip-flop circuit according to claim 1 comprising a source of second complementary clock signals, and wherein said second inverter means comprises clocked means which are enabled by said second complementary clock signals for reversing the polarity of the output of said delayed logical circuit means after an output is derived out from said delayed logical circuit means in synchronism with said first complementary clock signals.
Claim 11
Dependent Claim
77 words
A flip-flop circuit according to claim 7 which further comprises a first stabilizing circuit connected to the output of said delayed logic circuit means for holding the output voltage thereof for a predetermined length of time after said delayed logic circuit means has operated, and a second stabilizing circuit connected to the output of said second inverter means for holding the output voltage thereof for a predetermined length of time after said second inverter means has operated.
Claim 12
Dependent Claim
68 words
A flip-flop circuit according to claim 8 wherein each of said first and second stabilizing circuits comprises an inverter including a complementary pair of field effect transistors, and a clocked inverter including a complementary pair of field effect transistors, the input of said clocked inverter being connected to the output of said inverter and the output of said clocked inverter being connected to the input of said inverter.
Claim 13
Dependent Claim
46 words
A flip-flop circuit according to claim 8 wherein each of said first and second stabilizing circuits comprises an inverter including a complementary pair of field effect transistors, and a clocked inverter including a complementary pair of field effect transistors and connected in cascade with said inverter.
Claim 14
Dependent Claim
72 words
A flip-flop circuit according to claim 7 wherein said first and second clock signals have different frequencies and which further comprises a stabilizing circuit connected to the output of one of said delayed logic circuit means and said second inverter means, and being supplied with a clock signal have a lower frequency for holding the output of said one means for a predetermined length of time after said one means has operated.
Claim 15
Dependent Claim
41 words
A flip-flop circuit according to claim 11 wherein said stabilizing circuit comprises an inverter including a complementary pair of field effect transistors, and a clocked inverter including a complementary pair of field effect transistors and connected in cascade with said inverter.
Claim 16
Dependent Claim
63 words
A flip-flop circuit according to claim 11 wherein said stabilizing circuit comprises an inverter including a complementary pair of field effect transistors, and a clocked inverter including a complementary pair of field effect transistors, the input of said clocked inverter being connected to the output of said inverter and the output of said clocked inverter being connected to the input of said inverter.
Claim 17
Dependent Claim
447 words
A flip-flop circuit utilizing insulated gate field effect transistors, comprising: a source of first and second logical inputs; a source of operating voltage; a source of first complementary clock signals; first inverter means including a complementary pair of field effect transistors for receiving and reversing the polarity of said first logical input; delayed logic circuit means comprising first to fourth transistors of one channel type each including source and drain regions defining therebetween a conduction path and a gate electrode, and fifth to eighth transistors of the other channel type each including source and drain regions defining therebetween a conduction path and a gate electrode, the conduction paths of said first and second transistors being coupled in parallel, the conduction path of said third transistor being connected in series with that of said first transistor, the conduction paths of said fifth and sixth transistors being connected in series, the conduction path of said seventh transistor being arranged in parallel with serially connected conduction paths of said fifth and sixth transistors, the conduction path of said second transistor being connected in series with that of said seventh transistor, the conduction paths of said fourth and eighth transistors being connected in series between the conduction paths of said second and said seventh transistors, the conduction paths of said first, third, fourth, seventh and eighth transistors being connected in series across said source of operating voltage, the gate electrodes of said first and fifth transistors being connected in common to receive said second logical input, the gate electrodes of said second and sixth transistors being connected in common to receive the output of said flip-flop circuit, the gate electrodes of said third and seventh transistors being connected in common to receive the output of said first inverter means, the gate electrodes of said fourth and eighth transistors being connected to said clock signal source to receive respective complementary clock signals, and the junction between the conduction paths of said fourth and eighth transistors comprising an output of said delayed logic circuit means; and second inverter means coupled to the output of said delayed logic circuit means, and including a complementary pair of field effect transistors for receiving and reversing the polarity of the outputs of said delayed logic circuit means to provide the output of said flip-flop circuit; whereby when the states of first and second logical inputs are in a predetermined combination, the output state of the flip-flop circuit is held, and when the states of said first and second logical inputs are in other combinations, either one of said first and second logical inputs is dominantly derived out on the output side in response to said clock signals.
Claim 18
Dependent Claim
447 words
A flip-flop circuit utilizing insulated gate field effect transistors, comprising: a source of first and second logical inputs; a source of operating voltage; a source of first complementary clock signals; first inverter means including a complementary pair of field effect transistors for receiving and reversing the polarity of said first logical input; delayed logic circuit means comprising first to fourth transistors of one channel type each including source and drain regions defining therebetween a conduction path and a gate electrode, and fifth to eighth transistors of the other channel type each including source and drain regions defining therebetween a conduction path and a gate electrode, the conduction paths of said first and second transistors being coupled in parallel, the conduction path of said third transistor being connected in series with that of said first transistor, the conduction paths of said fifth and sixth transistors being connected in series, the conduction path of said seventh transistor being arranged in parallel with serially connected conduction paths of said fifth and sixth transistors, the conduction path of said second transistor being connected in series with that of said seventh transistor, the conduction paths of said fourth and eighth transistors being connected in series between the conduction paths of said second and said seventh transistors, the conduction paths of said first, third, fourth, seventh and eighth transistors being connected in series across said source of operating voltage, the gate electrodes of said first and fifth transistors being connected in common to receive said second logical input, the gate electrodes of said second and sixth transistors being connected in common to receive the output of said flip-flop circuit, the gate electrodes of said third and seventh transistors being connected in common to receive the output of said first inverter means, the gate electrodes of said fourth and eighth transistors being connected to said clock signal source to receive respective complementary clock signals, and the junction between the conduction paths of said fourth and eighth transistors comprising an output of said delayed logic circuit means; and second inverter means coupled to the output of said delayed logic circuit means, and including a complementary pair of field effect transistors for receiving and reversing the polarity of the outputs of said delayed logic circuit means to provide the output of said flip-flop circuit; whereby when the states of first and second logical inputs are in a predetermined combination, the output state of the flip-flop circuit is held, and when the states of said first and second logical inputs are in other combinations, either one of said first and second logical inputs is dominantly derived out on the output side in response to said clock signals.
Claim 19
Dependent Claim
66 words
A flip-flop circuit according to claim 14 comprising a source of second complementary clock signals, and wherein said second inverter means comprises clocked means which are enabled by said second complementary clock signals for reversing the polarity of the output of said delayed logical circuit means after an output is derived out from said delayed logical circuit means in synchronism with said first complementary clock signals.
Claim 20
Dependent Claim
77 words
A flip-flop circuit according to claim 15 which further comprises a first stabilizing circuit connected to the output of said delayed logic circuit means for holding the output voltage thereof for a predetermined length of time after said delayed logic circuit means has operated, and a second stabilizing circuit connected to the output of said second inverter means for holding the output voltage thereof for a predetermined length of time after said second inverter means has operated.
Claim 21
Dependent Claim
68 words
A flip-flop circuit according to claim 16 wherein each of said first and second stabilizing circuits comprises an inverter including a complementary pair of field effect transistors, and a clocked inverter including a complementary pair of field effect transistors, the input of said clocked inverter being connected to the output of said inverter and the output of said clocked inverter being connected to the input of said inverter.
Claim 22
Dependent Claim
46 words
A flip-flop circuit according to claim 16 wherein each of said first and second stabilizing circuits comprises an inverter including a complementary pair of field effect transistors, and a clocked inverter including a complementary pair of field effect transistors and connected in cascade with said inverter.
Claim 23
Dependent Claim
72 words
A flip-flop circuit according to claim 15 wherein said first and second clock signals have different frequencies and which fuRther comprises a stabilizing circuit connected to the output of one of said delayed logic circuit means and said second inverter means, and being supplied with a clock signal having a lower frequency for holding the output of said one means for a predetermined length of time after said one means has operated.
Claim 24
Dependent Claim
41 words
A flip-flop circuit according to claim 19 wherein said stabilizing circuit comprises an inverter including a complementary pair of field effect transistors, and a clocked inverter including a complementary pair of field effect transistors and connected in cascade with said inverter.
Claim 25
Dependent Claim
63 words
A flip-flop circuit according to claim 19 wherein said stabilizing circuit comprises an inverter including a complementary pair of field effect transistors, and a clocked inverter including a complementary pair of field effect transistors, the input of said clocked inverter being connected to the output of said inverter and the output of said clocked inverter being connected to the input of said inverter.
Claim 26
Dependent Claim
47 words
A flip-flop circuit according to claim 14 which further comprises a stabilizing circuit connected to the output of said delayed logic circuit means for holding the output voltage of said logic circuit means for a predetermined length of time after said delayed logic circuit means has operated.
Claim 27
Dependent Claim
63 words
A flip-flop circuit according to claim 22 wherein said stabilizing circuit comprises an inverter including a complementary pair of field effect transistors, and a clocked inverter having a complementary pair of field effect transistors, the input of said clocked inverter being connected to the output of said inverter and the output of said clocked inverter being connected to the input of said inverter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-02 | 1978-12-02 | 1979-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-02 | 1982-12-02 | 1983-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-02 | 1986-12-02 | 1987-06-03 | $7700.00 | Window Closed / Lapsed |