Logic interconnections

Claim 2

A dynamic logic interconnection for use as an inverter which is operated by periodically repeated single phase clock pulses comprising: a semiconductor pn- or metal-semiconductor junction diode having two electrodes; a field effect transistor having an insulated gate electrode and two current path electrodes for the controlled current path thereof; means for connecting one electrode of said diode to one of said current path electrodes of said field effect transistor so that said diode is connected in series with the controlled current path of said transistor; means for applying an input signal containing information to be inverted to said gate electrode of said transistor; means for applying a periodically repeated phase clock pulse to the free electrodes of said transistor and said diode; and means for collecting an output signal which contains the inverted input information between the individual phase clock pulses, said collecting means being connected to the junction between said transistor and said diode.

Claim 3

A dynamic logic interconnection as defined in claim 1, including means for connecting said diode in series with said transistor in such a manner that said diode is conducting when a negative phase clock pulse is applied to said free electrodes.

Claim 4

A dynamic logic interconnection, for use as a logic circuit which is operated by periodically repeated single phase clock pulses comprising: a semiconductor pn- or metal-semiconductor junction diode having two electrodes; a field effect transistor having an insulated gate electrode and two current path electrodes for the controlled current path thereof; means for connecting one electrode of said diode to one of said current path electrodes of said field effect transistor so that said diode is connected in series with the controlled current path of said transistor; means for applying a signal containing input information to said gate electrode of said transistor; means for applying a periodically repeated phase clock pulse to the free electrodes of said transistor and said diode; and means for collecting an output signal which contains the input information during a phase clock pulse, said collecting means being connected to the junction between said transistor and said diode.

Claim 5

A dynamic logic interconnection, for use as a logic circuit which is operated by periodically repeated single phase clock pulses comprising: a semiconductor pn- or metal-semiconductor junction diode having two electrodes; a field effect transistor having an insulated gate electrode and two current path electrodes for the controlled current path thereof; means for connecting one electrode of said diode to one of said current path electrodes of said field effect transistor so that said diode is connected in series with the controlled current path of said transistor; means for applying a signal containing input information to said gate electrode of said transistor; means for applying a periodically repeated phase clock pulse to the free electrodes of said transistor and said diode; and means for collecting an output signal which contains the input information during a phase clock pulse, said collecting means being connected to the junction between said transistor and said diode.

Claim 6

A dynamic logic interconnection as defined in claim 3, in which said field effect transistor is a MOS field effect transistor.

Claim 7

A dynamic logic interconnection as defined in claim 3, in which said field effect transistor is a depletion-layer field effect transistor.

Claim 8

A dynamic logic interconnection as recited in claim 3, including means for connecting said diode in series with said transistor in such a manner that said diode is cut-off when a negative phase clock pulse is applied to said free electrodes.

Claim 9

A dynamic logic interconnection which is operated by periodically repeated single phase clock pulses comprising: a semiconductor pn- or metal-semiconductor junction diode having two electrodes; a field effect transistor having an insulated gate electrode and two current path electrodes for the controlled current path thereof; means for connecting one electrode of said diode to one of said current path electrodes of said field effect transistor so that said diode is connected in series with the controlled current path of said transistor; means for applying a signal containing input information to the other current path electrode of said transistor; means for applying a periodically repeated phase clock pulse to said gate electrode of said transistor and the other electrode of said diode, said means for connecting one electrode of said diode to one of said current path electrodes connecting said diode in series with said transistor in such a manner that said diode is conducting when a negative phase clock pulse is applied to said gate and diode electrodes; and means for collecting an output signal which contains the input information between the individual phase clock pulses, said collecting means being connected to the junction between said transistor and said diode.

Claim 10

A dynamic logic interconnection which is operated by periodically repeated single phase clock pulses comprising: a semiconductor pn- or metal-semiconductor junction diode having two electrodes; a field effect transistor having an insulated gate electrode and two current path electrodes for the controlled current path thereof; means for connecting one electrode of said diode to one of said current path electrodes of said field effect transistor so that said diode is connected in series with the controlled current path of said transistor; means for applying a signal containing input information to the other current path electrode of said transistor; means for applying a periodically repeated phase clock pulse to said gate electrode of said transistor and the other electrode of said diode, said means for connecting one electrode of said diode to one of said current path electrodes connecting said diode in series with said transistor in such a manner that said diode is conducting when a negative phase clock pulse is applied to said gate and diode electrodes; and means for collecting an output signal which contains the input information between the individual phase clock pulses, said collecting means being connected to the junction between said transistor and said diode.

Claim 11

A dynamic logic interconnection for use as an OR interconnection which is operated by periodically repeated single phase clock pulses comprising: a semiconductor pn- or metal-semiconductor junction diode having two electrodes; a field effect transistor having an insulated gate electrode and two current path electrodes for the controlled current path thereof; means for connecting one electrode of said diode to one of said current path electrodes of said field effect transistor so that said diode is connected in series with the controlled current path of said transistor; a further field effect transistor having an insulated gate electrode, said further field effect transistor having its controlled current path connected in parallel with the controlled current path of said first mentioned field effect transistor; means for applying respective signals containing input information to the respective gate electrodes of said field effect transistors; means for applying a periodically repeated phase clock pulse to the free electrode of said diode and the free electrodes of said field effect transistors; and means for collecting a signal which contains output information between the individual phase clock pulses, said collecting means being connected to the junction between said diode and said field effect transistors.

Claim 12

A dynamic logic interconnection for use as an OR interconnection which is operated by periodically repeated single phase clock pulses comprising: a semiconductor pn- or metal-semiconductor junction diode having two electrodes; a field effect transistor having an insulated gate electrode and two current path electrodes for the controlled current path thereof; means for connecting one electrode of said diode to one of said current path electrodes of said field effect transistor so that said diode is connected in series with the controlled current path of said transistor; a further field effect transistor having an insulated gate electrode, said further field effect transistor having its controlled current path connected in parallel with the controlled current path of said first mentioned field effect transistor; means for applying respective signals containing input information to the respective gate electrodes of said field effect transistors; means for applying a periodically repeated phase clock pulse to the free electrode of said diode and the free electrodes of said field effect transistors; and means for collecting a signal which contains output information between the individual phase clock pulses, said collecting means being connected to the junction between said diode and said field effect transistors.

Claim 13

A dynamic logic interconnection as defined in claim 8, including means for connecting said diode in series with said field effect transistors in such a manner that said diode is conducting when a negative phase clock pulse is applied to said free electrodes whereby said logic interconnection is a negated OR interconnection.

Claim 14

A dynamic logic interconnection as defined in claim 8, including means for connecting said diode in series with said field effect transistors in such a manner that said diode is cut-off when a negative phase clock pulse is applied to said free electrodes.

Claim 15

A dynamic logic interconnection which is operated by periodically repeated single phase clock pulses comprising: a semiconductor pn- or metal-semiconductor junction diode having two electrodes; a field effect transistor having an insulated gate electrode and two current path electrodes for the controlled current path thereof; means for connecting one electrode of said diode to one of said current path electrodes of said field effect transistor so that said diode is connected in series with the controlled current path of said transistor; two additional field effect transistors with insulated gate electrodes, said additional field effect transistors having their controlled current paths connected in series, said first mentioned field effect transistor having its controlled current path connected in parallel with the controlled current paths of said two additional field effect transistors; means for applying respective signals containing input information to the respective gate electrodes of said field effect transistors; means for collecting a signal containing output information from the junction between said diode and said first mentioned field effect transistor; and means for applying a periodically repeated phase clock pulse to the other electrode of said dIode and the other current path electrode of said first mentioned field effect transistor.

Claim 16

A dynamic logic interconnection which is operated by periodically repeated single phase clock pulses comprising: a semiconductor pn- or metal-semiconductor junction diode having two electrodes; a field effect transistor having an insulated gate electrode and two current path electrodes for the controlled current path thereof; means for connecting one electrode of said diode to one of said current path electrodes of said field effect transistor so that said diode is connected in series with the controlled current path of said transistor; two additional field effect transistors with insulated gate electrodes, said additional field effect transistors having their controlled current paths connected in series, said first mentioned field effect transistor having its controlled current path connected in parallel with the controlled current paths of said two additional field effect transistors; means for applying respective signals containing input information to the respective gate electrodes of said field effect transistors; means for collecting a signal containing output information from the junction between said diode and said first mentioned field effect transistor; and means for applying a periodically repeated phase clock pulse to the other electrode of said dIode and the other current path electrode of said first mentioned field effect transistor.

Claim 17

A dynamic logic interconnection which is operated by periodically repeated single phase clock pulses comprising: a semiconductor pn- or metal-semiconductor junction diode having two electrodes; a field effect transistor having an insulated gate electrode and two current path electrodes for the controlled current path thereof; means for connecting one electrode of said diode to one of said current path electrodes of said field effect transistor so that said diode is connected in series with the controlled current path of said transistor; means for applying signals containing input information to the gate electrode of said field effect transistor; and means for applying a periodically repeated phase clock pulse to the other electrode of said diode and the other current path electrode of said field effect transistor, said signals containing input information being applied at least for the duration of a phase clock pulse.

Claim 18

A dynamic logic interconnection which is operated by periodically repeated single phase clock pulses comprising: a semiconductor pn- or metal-semiconductor junction diode having two electrodes; a field effect transistor having an insulated gate electrode and two current path electrodes for the controlled current path thereof; means for connecting one electrode of said diode to one of said current path electrodes of said field effect transistor so that said diode is connected in series with the controlled current path of said transistor; means for applying signals containing input information to the gate electrode of said field effect transistor; and means for applying a periodically repeated phase clock pulse to the other electrode of said diode and the other current path electrode of said field effect transistor, said signals containing input information being applied at least for the duration of a phase clock pulse.

Claim 19

A dynamic logic interconnection which is operated by periodically repeated single phase clock pulses comprising: a semiconductor pn- or metal-semiconductor junction diode having two electrodes; a field effect transistor having an insulated gate electrode and two current path electrodes for the controlled current path thereof; means for connecting one electrode of said diode to one of said current path electrodes of said field effect transistor so that said diode is connected in series with the controlled current path of said transistor; means for applying signals containing input information to the gate electrode of said field effect transistor; and means for applying a periodically repeated phase clock pulse to the free electrode of said diode and the free electrode of said field effect transistor, said signals containing input information starting, in time, during a phase clock pulse.

Claim 20

A dynamic logic interconnection which is operated by periodically repeated single phase clock pulses comprising: a semiconductor pn- or metal-semiconductor junction diode having two electrodes; a field effect transistor having an insulated gate electrode and two current path electrodes for the controlled current path thereof; means for connecting one electrode of said diode to one of said current path electrodes of said field effect transistor so that said diode is connected in series with the controlled current path of said transistor; means for applying signals containing input information to the gate electrode of said field effect transistor; and means for applying a periodically repeated phase clock pulse to the free electrode of said diode and the free electrode of said field effect transistor, said signals containing input information starting, in time, during a phase clock pulse.

Claim 21

A dynamic logic interconnection as defined in claim 13, in which the discharge time constant of said diode is less than that of said field effect transistor.