US4479191A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit with interruptable oscillator circuit
Assignee: Toshiba Corp
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Filing: 1981-07-13
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Granted: 1984-10-23
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Expires: 2001-07-13
Abstract
Abstract A semiconductor integrated circuit which is capable of being selectively set to an operation mode or a stand-by mode has an oscillating circuit for outputting a frequency signal for controlling the operation of said semiconductor circuit. The output side of the oscillating circuit is connected to a timing generator through a first NAND gate. To the other input terminal of the first NAND gate is supplied information of an oscillation stop request (stand-by mode) due to reduction of the voltage of a power supply connected to the outside of the semiconductor integrated circuit and an oscillation start request (operation mode) accompanying the recovery of the voltage supply circuit or the oscillation from the timing generator through a second NAND gate. Thus, when the supply voltage is reduced, a logic low level signal is supplied from the second NAND gate to the first NAND gate to block the output of the oscillating circuit. A counter is connected to the oscillating circuit. When the supply voltage is recovered, the output of the oscillating circuit is supplied to the counter to be counted thereby. After the count reaches a predetermined number corresponding to a period sufficient to obtain a stable oscillation frequency output, an H flag is reset by a carry from the counter, whereupon a signal from the H Flag is supplied to the timing generator to cause the resumption of the operation of the timing generator.
Inventors
- 👤 Minejiro Nojima
- 👤 Makiji Kobayashi
- 👤 Atsushi Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:32
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3206; G06F1/3228; H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/03
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
151 words
A semiconductor integrated circuit capable of being selectively set to an operation mode and a stand-by mode comprising: (a) oscillator means for generating an oscillation signal when an enable signal indicates that said semiconductor integrated circuit is in said operation mode and for not generating an oscillation signal when said enable signal indicates that said semiconductor integrated circuit is in said stand-by mode; (b) timing generator means coupled to said oscillator means for generating, in response to said oscillation signal, timing signals for said semiconductor integrated circuit and for generating an oscillation block signal in response to a first signal supplied from said semiconductor integrated circuit; and (c) gate means coupled to said oscillator means for outputting said enable signal, said gate means having one input receiving a second signal indicating the onset of said stand-by mode and a second input receiving said oscillation block signal from said timing generator means.
Claim 2
Dependent Claim
151 words
A semiconductor integrated circuit capable of being selectively set to an operation mode and a stand-by mode comprising: (a) oscillator means for generating an oscillation signal when an enable signal indicates that said semiconductor integrated circuit is in said operation mode and for not generating an oscillation signal when said enable signal indicates that said semiconductor integrated circuit is in said stand-by mode; (b) timing generator means coupled to said oscillator means for generating, in response to said oscillation signal, timing signals for said semiconductor integrated circuit and for generating an oscillation block signal in response to a first signal supplied from said semiconductor integrated circuit; and (c) gate means coupled to said oscillator means for outputting said enable signal, said gate means having one input receiving a second signal indicating the onset of said stand-by mode and a second input receiving said oscillation block signal from said timing generator means.
Claim 3
Dependent Claim
26 words
A semiconductor integrated circuit according to claim 1 further comprising a latch circuit coupled to said timing generator means for generating and storing said first signal.
Claim 4
Dependent Claim
27 words
A semiconductor integrated circuit according to claim 2 further comprising means for detecting said second signal and for causing said latch circuit to generate said first signal.
Claim 5
Dependent Claim
17 words
A semiconductor integrated circuit according to claim 3 wherein said detecting and causing means includes a decoder.
Claim 6
Dependent Claim
202 words
A semiconductor integrated circuit capable of being set to an operation mode or a stand-by mode comprising: (a) oscillator means for providing a pulsed oscillation signal when an enable signal indicates that said semiconductor integrated circuit is in said operation mode and for not generating an oscillation signal when said enable signal indicates that said semiconductor integrated circuit is in said stand-by mode; (b) timing generator means coupled to said oscillator means for generating, in response to said oscillation signal and a timing means enable signal, timing signals for a said semiconductor integrated circuit and for generating an oscillation block release signal in response to a first signal; (c) gate means coupled to said oscillator means and said timing generator means for outputting said enable signal, said gate means having one input receiving a second signal indicating the end of said stand-by mode and a second input receiving said oscillation block release signal from said timing generator means; and (d) counter means coupled to said oscillator means and said timing generator means for counting a predetermined number of pulses of said oscillation signal and for generating said timing means enable signal to allow said timing generator means to generate said timing signals.
Claim 7
Dependent Claim
202 words
A semiconductor integrated circuit capable of being set to an operation mode or a stand-by mode comprising: (a) oscillator means for providing a pulsed oscillation signal when an enable signal indicates that said semiconductor integrated circuit is in said operation mode and for not generating an oscillation signal when said enable signal indicates that said semiconductor integrated circuit is in said stand-by mode; (b) timing generator means coupled to said oscillator means for generating, in response to said oscillation signal and a timing means enable signal, timing signals for a said semiconductor integrated circuit and for generating an oscillation block release signal in response to a first signal; (c) gate means coupled to said oscillator means and said timing generator means for outputting said enable signal, said gate means having one input receiving a second signal indicating the end of said stand-by mode and a second input receiving said oscillation block release signal from said timing generator means; and (d) counter means coupled to said oscillator means and said timing generator means for counting a predetermined number of pulses of said oscillation signal and for generating said timing means enable signal to allow said timing generator means to generate said timing signals.
Claim 8
Dependent Claim
26 words
A semiconductor integrated circuit according to claim 5 further comprising a latch circuit coupled to said timing generator means for generating and storing said first signal.
Claim 9
Dependent Claim
27 words
A semiconductor integrated circuit according to claim 6, further comprising means for detecting said second signal and for causing said latch circuit to generate said first signal.
Claim 10
Dependent Claim
17 words
A semiconductor integrated circuit according to claim 7, wherein said detecting and causing means includes a decoder.
Claim 11
Dependent Claim
259 words
An operational control system including a high integration density semiconductor element capable of being selectively set to an operation mode and a stand-by mode, said system comprising: (a) a memory for storing operational control instructions; (b) decoder means coupled to said memory for decoding said operational control instructions read from said memory and for producing control signals; (c) a data bus for providing data transfer; (d) an input/output port coupled to said data bus for inputting and outputting data on said bus; (e) arithmetic and logic means coupled to said data bus for performing arithmetic and logic operations on data appearing on said data bus; (f) oscillator means for generating an oscillation signal when an enable signal indicates that said operational control system is in said operation mode and for not generating an oscillation signal when said enable signal indicates that said operational control system is in said stand-by mode; (g) timing generator means coupled to said oscillator means and said data bus generating, in response to said oscillation signal, timing signals for use by said operational control system and for generating an oscillation block signal in response to a first signal supplied via said data bus in response to one of said control signals; and (h) gate means coupled to said oscillator means and said timing generator means for outputting said enable signal, said gate means having one input receiving, from said input/output port, a second signal indicating the onset of said stand-by mode and a second input receiving said oscillation block signal from said timing generator means.
Claim 12
Dependent Claim
259 words
An operational control system including a high integration density semiconductor element capable of being selectively set to an operation mode and a stand-by mode, said system comprising: (a) a memory for storing operational control instructions; (b) decoder means coupled to said memory for decoding said operational control instructions read from said memory and for producing control signals; (c) a data bus for providing data transfer; (d) an input/output port coupled to said data bus for inputting and outputting data on said bus; (e) arithmetic and logic means coupled to said data bus for performing arithmetic and logic operations on data appearing on said data bus; (f) oscillator means for generating an oscillation signal when an enable signal indicates that said operational control system is in said operation mode and for not generating an oscillation signal when said enable signal indicates that said operational control system is in said stand-by mode; (g) timing generator means coupled to said oscillator means and said data bus generating, in response to said oscillation signal, timing signals for use by said operational control system and for generating an oscillation block signal in response to a first signal supplied via said data bus in response to one of said control signals; and (h) gate means coupled to said oscillator means and said timing generator means for outputting said enable signal, said gate means having one input receiving, from said input/output port, a second signal indicating the onset of said stand-by mode and a second input receiving said oscillation block signal from said timing generator means.
Claim 13
Dependent Claim
29 words
An operation control system according to claim 9 further comprising a latch circuit coupled to said timing generator means and to said data bus for storing said first signal.
Claim 14
Dependent Claim
40 words
An operational control system according to claim 9 further including threshold means coupled to said input/output port for generating said second signal indicates when a power supply voltage for said operation control system is lower than a predetermined threshold level.
Claim 15
Dependent Claim
310 words
An operational control system including a high integration density semiconductor element capable of being selectively set to an operation mode and a stand-by mode, said system comprising: (a) a memory for storing operational control instructions; (b) decoder means coupled to said memory for decoding said operation control instructions read from said memory to produce control signals; (c) a data bus for data transfer; (d) an input/output port coupled to said data bus for inputting and outputting data on said bus; (e) arithmetic and logic unit means coupled to said data bus for performing arithmetic and logic operations on data appearing on said data bus; (f) oscillator means for generating a pulse oscillation signal when an enable signal indicates that said operational control system is in said operation mode and for not generating an oscillation signal when said enable signal indicates that said operational control system is in said stand-by mode; (g) timing generator means coupled to said oscillator means for generating, in response to said oscillation signal and a timing generator enable signal, timing signals for said operational control system and for generating an oscillation block release signal in response to a first signal supplied via from said data bus in response to one of said control signals; (h) gate means coupled to said oscillator means, said input/output port, and said timing generator means, for outputting said enable signal, said gate means having one input receiving, from said input/output port, a second signal indicating the end of said stand-by mode and a second input receiving said oscillation block release signal from said timing generator means; and (i) counter means coupled to said oscillator means and said timing generator means for counting a predetermined number of pulses of said oscillation signal and then for generating a timing means enable signal to allow said timing generator means to generate said timing signals.
Claim 16
Dependent Claim
310 words
An operational control system including a high integration density semiconductor element capable of being selectively set to an operation mode and a stand-by mode, said system comprising: (a) a memory for storing operational control instructions; (b) decoder means coupled to said memory for decoding said operation control instructions read from said memory to produce control signals; (c) a data bus for data transfer; (d) an input/output port coupled to said data bus for inputting and outputting data on said bus; (e) arithmetic and logic unit means coupled to said data bus for performing arithmetic and logic operations on data appearing on said data bus; (f) oscillator means for generating a pulse oscillation signal when an enable signal indicates that said operational control system is in said operation mode and for not generating an oscillation signal when said enable signal indicates that said operational control system is in said stand-by mode; (g) timing generator means coupled to said oscillator means for generating, in response to said oscillation signal and a timing generator enable signal, timing signals for said operational control system and for generating an oscillation block release signal in response to a first signal supplied via from said data bus in response to one of said control signals; (h) gate means coupled to said oscillator means, said input/output port, and said timing generator means, for outputting said enable signal, said gate means having one input receiving, from said input/output port, a second signal indicating the end of said stand-by mode and a second input receiving said oscillation block release signal from said timing generator means; and (i) counter means coupled to said oscillator means and said timing generator means for counting a predetermined number of pulses of said oscillation signal and then for generating a timing means enable signal to allow said timing generator means to generate said timing signals.
Claim 17
Dependent Claim
29 words
An operational control system according to claim 12 further comprising a latch circuit coupled to said timing generator means and to said data bus for storing said first signal.
Claim 18
Dependent Claim
38 words
An operational control system according to claim 12 further including threshold means coupled to said input/output port for generating said second signal when a power supply voltage of said operational control system has exceeded a predetermined threshold level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-10-23 | 1988-04-23 | 1988-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-10-23 | 1992-04-23 | 1992-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-10-23 | 1996-04-23 | 1996-10-23 | $7700.00 | Window Closed / Lapsed |