US3623017A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dual clocking arrangement for a digital computer
Assignee: Unisys Corp
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Filing: 1969-10-22
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Granted: 1971-11-23
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Expires: 1989-10-22
Abstract
Abstract In most general purpose digital computers, there are some instructions that require a relatively long execution time. Some examples of these extended sequence instructions would be multiply, divide, square root, etc. When starting the execution of this type of instruction, it is necessary to interrupt the normal timing of the computer and to implement an ''''arithmetic hold'''' condition which, in effect, keeps the computer from fetching a new instruction while the extended sequence instruction is being executed. In the present invention, two 4phase different-speed clocks are utilized. The pulse repetition rate of the first low-speed clock may be substantially less than that of the second high-speed clock. Suitable control circuits are provided for sensing when an extended sequence-type instruction is involved and for switching in the high-speed clock such that the extended sequence instruction is executed at a higher rate than is a normal instruction.
Inventors
- 👤 William P Lowell
- 👤 Harry W Moore
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:13
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/08; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3867; G06F9/3869
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
182 words
In a digital computer having a memory section for storing operands and instructions, said instructions being of first and second types, an input-output section, an arithmetic section an improved control section comprising: an instruction register for at least temporarily storing an instruction; decoding means adapted to receive signals from said instruction register for producing a first control signal when the instruction in said instruction register is of said first type and a second control signal when the instruction in said instruction register is of said second type; first and second clock pulse signal generating means, said second clock pulse signal generating means having a pulse repetition rate substantially greater than that of said first clock pulse signal generating means; and switching means controlled by said first and second control signal adapted to receive the output signals from said first and second clock-pulse signal-generating means for selectively applying the output from said first or second clock-pulse signal-generating means to said arithmetic section such that instructions of said second type will be executed at a substantially greater rate than instructions of said first type.
Claim 2
Dependent Claim
182 words
In a digital computer having a memory section for storing operands and instructions, said instructions being of first and second types, an input-output section, an arithmetic section an improved control section comprising: an instruction register for at least temporarily storing an instruction; decoding means adapted to receive signals from said instruction register for producing a first control signal when the instruction in said instruction register is of said first type and a second control signal when the instruction in said instruction register is of said second type; first and second clock pulse signal generating means, said second clock pulse signal generating means having a pulse repetition rate substantially greater than that of said first clock pulse signal generating means; and switching means controlled by said first and second control signal adapted to receive the output signals from said first and second clock-pulse signal-generating means for selectively applying the output from said first or second clock-pulse signal-generating means to said arithmetic section such that instructions of said second type will be executed at a substantially greater rate than instructions of said first type.
Claim 3
Dependent Claim
168 words
In a digital computer having a memory section for storing instructions of first and second types, an input-output section, an arithmetic section, an improved control section comprising: means for at least temporarily storing an instruction; means coupled to said instruction storing means for producing a first control signal when the instruction in said instruction storing means is of said first type and a second control signal when the instruction in said instruction storing means is of said second type; first and second clock-pulse signal-generating means, said second clock-pulse signal-generating means having a pulse repetition rate substantially greater than that of said first clock-pulse signal-generating means; and switching means controlled by said first and second control signal adapted to receive the output signals from said first and second clock-pulse signal-generating means for selectively applying the output from said first or second clock-pulse signal-generating means to said arithmetic section such that instructions of said second type will be executed at a substantially greater rate than instructions of said first type.
Claim 4
Dependent Claim
168 words
In a digital computer having a memory section for storing instructions of first and second types, an input-output section, an arithmetic section, an improved control section comprising: means for at least temporarily storing an instruction; means coupled to said instruction storing means for producing a first control signal when the instruction in said instruction storing means is of said first type and a second control signal when the instruction in said instruction storing means is of said second type; first and second clock-pulse signal-generating means, said second clock-pulse signal-generating means having a pulse repetition rate substantially greater than that of said first clock-pulse signal-generating means; and switching means controlled by said first and second control signal adapted to receive the output signals from said first and second clock-pulse signal-generating means for selectively applying the output from said first or second clock-pulse signal-generating means to said arithmetic section such that instructions of said second type will be executed at a substantially greater rate than instructions of said first type.
Claim 5
Dependent Claim
155 words
In a digital computer having a memory for storing operands and instructions, said instructions being of first and second types, and an arithmetic section, an improved control section comprising: means for storing instruction words read out from said memory means connected to said instruction storage means for producing a predetermined signal when said instruction is of said first type first and second clock-pulse generators for producing clock-pulse signals for said computer at first and second rates respectively command generator means adapted to receive regularly occurring clock pulse signals and signals determined by said instruction word for producing command enable signals for controlling the operation of said computer switching means connected to receive the output from said first and second clock-pulse generators controlled by said predetermined signal for selectively connecting the clock-pulse signals to said command generator such that said command enable signals are produced at differing rates depending upon the type of instruction undergoing processing.
Claim 6
Dependent Claim
155 words
In a digital computer having a memory for storing operands and instructions, said instructions being of first and second types, and an arithmetic section, an improved control section comprising: means for storing instruction words read out from said memory means connected to said instruction storage means for producing a predetermined signal when said instruction is of said first type first and second clock-pulse generators for producing clock-pulse signals for said computer at first and second rates respectively command generator means adapted to receive regularly occurring clock pulse signals and signals determined by said instruction word for producing command enable signals for controlling the operation of said computer switching means connected to receive the output from said first and second clock-pulse generators controlled by said predetermined signal for selectively connecting the clock-pulse signals to said command generator such that said command enable signals are produced at differing rates depending upon the type of instruction undergoing processing.
Claim 7
Dependent Claim
29 words
Apparatus as in claim 3 wherein said first clock-pulse generator has a pulse repetition rate in the range of 3 to 5 times that of said second clock-pulse generator.
References Cited (Backward Citations)
US2840305A
Cited
USRE26087E
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-22 | 1975-05-24 | 1975-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-22 | 1979-05-24 | 1979-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-22 | 1983-05-24 | 1983-11-23 | $7700.00 | Window Closed / Lapsed |