CMOS single chip microprocessor

Claim 2

A CMOS single chip microprocessor which comprises an oscillator and a timing generator for operating internal circuits and is responsive to an operation control signal of a fixed cycle period to alternately execute a holding operation in which said oscillator and said timing generator are stopped, and a normal operation in which said oscillator and said timing generator operate to cause said internal circuits to perform program processings, said microprocessor comprising: first means (50) for producing command signals (COM1 to COM4) in accordance with said program processings; and second means (53 to 59, 68 to 72) connected to receive said command signals and said operation control signal (HOLD) for stopping the operations of said oscillator (62) and said timing generator (60) in response to the command signals and restarting the operations of said oscillator (62) and said timing generator (60) in response to a transition of the operation control signal (HOLD) from a first level to a second level.

Claim 3

A microprocessor according to claim 1, characterized in that the operation control signal (HOLD) is supplied by an external oscillator through an external terminal (51).

Claim 4

A microprocessor according to claim 1, characterized in that said second means is arranged to stop successively said timing generator (60) and said oscillator (62) in response to said command signals (COM1, COM2) and to restart successively said oscillator (62) and said timing generator (60) in response to the level transition of the operation control signal (HOLD).

Claim 5

A microprocessor according to claim 3, characterized in that the time interval from a time when said oscillator (62) restrats its operation to a time when said timing generator (60) restarts its operation is determined on the basis of a warm-up time of said oscillator (62).

Claim 6

A microprocessor according to claim 1, characterized in that said first means (50) is arranged to produce first to fourth command signals (COM1 to COM4) in accordance with the program processings, and wherein said second means includes: a flip-flop circuit (55) which is set by the first command signal (COM1) to stop said timing generator (60); first circuit means (53, 54) for detecting the transition of the operation control signal (HOLD) from the first level to the second level in response to the second command signal (COM2) and the operation control signal; second circuit means (56, 57, 58, 61) responsive to said flip-flop circuit (55) and said first circuit means (53, 54) for stopping said oscillator (62) after said flip-flop circuit (55) has been set and starting said oscillator upon detection of the level transition of the operation control signal by said first circuit means when said flip-flop circuit is set; third circuit means (59, -68, 69) for frequency- dividing an output signal of said oscillator to provide a plurality of frequency-divided outputs; and fourth circuit means (70, 71, 72) responsive to the third and fourth command signals (COM3, COM4) to select one of the divided outputs of said third circuit means to reset said flip-flop circuit (55) by a selected divided output, thereby making said timing generator (60) operative.