EP0385567A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Clock signal generator for a data processing system
Assignee: International Business Machines Corp
•
Filing: 1990-01-18
•
Granted: —
•
Expires: 2010-01-18
Abstract
Abstract A clock signal generator for generating the system clock signal 24 for the processor 12 of a data processing system has a programmable frequency generator 30, 32, 34 which can be connected to a source of a fundamental frequency and connected 38 to receive control data 36 from the processor such the frequency of the system clock signal for the processor is programmable in response to data supplied by said processor under program control. The clock signal generator also includes additional programmable frequency generators connectable to receive control data from said processor under program control for generating additional, independent, programmable clock signals. In the example described each programmable frequency generator comprises a programmable phase-locked loop 32 and one or more programmable frequency dividers 34.
Inventors
- 👤 Brian Clive Homewood
- 👤 Malcolm Douglas Buttimer
- 👤 Roderick Michael Peters West
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 01:12
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/183; G; G06; G06F; G06F1/00; G06F1/04; G06F1/08; H03L7/22; H03L7/23
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
166 words
Clock signal generator for generating the system clock signal (24) for the processor (12) of a data processing system (26), the clock signal generator comprising a programmable frequency generator (23) which is connectable (50) to a source of a fundamental frequency (18) for generating the system clock signal and which is connectable (38, 40) to receive control data from the processor under program control whereby the frequency of the system clock signal (24) for the processor is selectable in response to data supplied by the processor (12) under program control, characterised in that the clock signal generator comprises one or more additional programmable frequency generators (19, 21), each additional programmable frequency generator being connectable (50) to the source of a fundamental frequency (18) and connectable (38, 40) to receive control data from said processor under program control for generating an additional independent clock signal, the frequency (20, 22) of each of which is selectable in response to data supplied by said processor (12) under program control.
Claim 2
Dependent Claim
166 words
Clock signal generator for generating the system clock signal (24) for the processor (12) of a data processing system (26), the clock signal generator comprising a programmable frequency generator (23) which is connectable (50) to a source of a fundamental frequency (18) for generating the system clock signal and which is connectable (38, 40) to receive control data from the processor under program control whereby the frequency of the system clock signal (24) for the processor is selectable in response to data supplied by the processor (12) under program control, characterised in that the clock signal generator comprises one or more additional programmable frequency generators (19, 21), each additional programmable frequency generator being connectable (50) to the source of a fundamental frequency (18) and connectable (38, 40) to receive control data from said processor under program control for generating an additional independent clock signal, the frequency (20, 22) of each of which is selectable in response to data supplied by said processor (12) under program control.
Claim 3
Dependent Claim
30 words
A clock signal generator as claimed in claim 1 wherein the or each programmable frequency generator comprises a programmable phase-locked loop (42, 44, 46) for generating a primary frequency (P).
Claim 4
Dependent Claim
97 words
A clock signal generator as claimed in claim 3 wherein the programmable phase-locked loop comprises a voltage controlled oscillator (46) for generating the primary frequency (P), a counter (42) for counting a number of cycles of said primary frequency, which number is determined by the control data, and for generating a control pulse on counting said number of cycles and a phase comparator (44) for comparing the phase of said control pulse to the phase of a reference frequency derived from said fundamental frequency, the phase comparator controlling the frequency of oscillation of the voltage controlled oscillator.
Claim 5
Dependent Claim
48 words
A clock signal generator as claimed in claim 2 or claim 3 wherein each programmable frequency generator comprises one or more programmable frequency dividers (34), each for selecting a sub-multiple of the primary frequency under program control as a separate clock signal output of that programmable frequency divider.
Claim 6
Dependent Claim
71 words
A clock signal generator as claimed in claim 4 wherein a programmable frequency divider (34) comprises a frequency divider chain (52, 54, 56) connected to receive the primary frequency (P) for generating sub-multiples of the primary frequency (P) and a multiplexer (58), responsive to the control data for selecting one of the submultiples of the primary frequency (P) under program control as the clock signal output of the programmable frequency generator.
Claim 7
Dependent Claim
41 words
A clock signal generator as claimed in any of claims 4 or 5 comprising means (60) for updating the selection of a sub-multiple of the primary frequency (P) by said multiplexer in synchronism with the slowest sub-harmonic input to the multiplexer.
Claim 8
Dependent Claim
26 words
A clock signal generator as claimed in any of the preceding claims wherein each programmable frequency generator comprises register means (36) for storing said control data.
Claim 9
Dependent Claim
24 words
A clock signal generator as claimed in any of the preceding claims wherein the programmable frequency generators are integrated in a single integrated circuit.
Claim 10
Dependent Claim
19 words
A data processing system comprising a system processor and a clock signal generator as claimed in any preceding claim.
Claim 11
Dependent Claim
53 words
A data processing system as claimed in claim 9 comprising control means (41, 43, 39) for initially setting the programmable frequency generator for generating said system clock signal to a predetermined initial frequency on system initialization, and stored system start-up code for, under processor control, changing said initial frequency to an operating frequency.
Claim 12
Dependent Claim
90 words
A data processing system as claimed in claim 9 or claim 10 in the form of a display adapter (92) for attachment of a display device (93) to the main bus (90) of a workstation, wherein the processor (12) is a display processor and wherein the system clock signal (24) is the system clock signal for the display processor, and wherein the clock signal generator (10) additionally generates programmable pixel clock signals and/or programmable clock signals controlling the display device and/or for scanning display data to the display device (93).
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.