Method and apparatus for changing the operating clock speed of a computer system

Claim 1

In a computer system having a signal bus, a memory, a central processing unit (CPU) and means for generating a plurality of clock signals of different frequencies, the CPU having an operating clock input and a plurality of internal registers, the CPU and memory being coupled to the bus, an apparatus for changing the operating clock of the computer system to activate and deactivate a doze mode of the system, said apparatus comprising; an input port for receiving a change frequency interrupt signal and for communicating the change frequency interrupt signal to the CPU via the bus; a plurality of output ports coupled to the bus, for outputting signals from the CPU via the bus; instructing means coupled to the bus for causing the CPU to: (i) store contents of the internal registers into the memory; (ii) generate and send to the output ports a frequency select signal; (iii) generate and send to the output ports a reset signal that resets the CPU; and (iv) reload the contents stored in the memory into the registers of the CPU after the CPU has been reset; latching means having a clock input, a data input, and a data output, said latching means for receiving from the output ports the reset signal at the clock input and the frequency select signal at the data input, and outputting the frequency select signal at the data output upon each occurrence of the reset signal; and gating means having a select input, a gate output, and a plurality of gate inputs coupled for receiving the clock signals, said gating means receiving at the select input the frequency select signal from the output of the latching means and gating one of the clock signals to the gate output that is coupled to the operating clock input of the CPU.