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US5041964A
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US
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Low-power, standby mode computer
Assignee: Samsung Electronics Co Ltd
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Filing: 1989-09-28
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Granted: 1991-08-20
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Expires: 2009-09-28
Abstract
Abstract A method and apparatus for configuring a computer in a low-power mode are provided. In the low-power mode, dynamic random access memory is refreshed by a battery powered system in order to maintain the memory contents. Low-power mode is entered by saving an interrupt mask and by disabling interrupts, followed by saving the DMA status, finishing DMA operations, and disabling DMA. After these steps, the I/O state of the machine is saved by saving various I/O registers and ports. A referesh of the memory is forced before the system refresh operations are discontinued.
Inventors
- 👤 James F. Cole
- 👤 James H. McNamara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:48
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3206; G06F1/3228; G06F9/00; G06F9/06; G06F9/46; G06F9/461; G06F9/463
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
222 words
A method usable for configuring a data processor to enter a low-power mode, said data processor including a CPU, a programmable interrupt controller coupled to said CPU, a direct memory access controller, I/O state indicating registers coupled to said CPU, I/O ports coupled to said CPU, a dynamic random access memory coupled to said direct memory access controller and to said CPU, and a system control chip coupled to said CPU having an unclocked sleep mode and an unpowered standby mode, the method comprising: receiving in said CPU a command to enter low-power mode; configuring said programmable interrupt controller, using said CPU, to disable acceptance of later interrupts; configuring said direct memory access controller, using said CPU, to disable later direct memory access operations wherein said configuring of said direct memory access controller occurs at a time following said step of configuring said programmable interrupt controller; saving, to said memory, the contents of at least some of said I/O state indicating registers and I/O ports, using said CPU, wherein said saving to said memory access at a time following said step of configuring said direct memory access controller; refreshing said memory, using said CPU, wherein said refreshing of said memory occurs at a time following said step of saving; and initiating said standby mode of said system control chip using said CPU.
Claim 2
Independent Claim
222 words
A method usable for configuring a data processor to enter a low-power mode, said data processor including a CPU, a programmable interrupt controller coupled to said CPU, a direct memory access controller, I/O state indicating registers coupled to said CPU, I/O ports coupled to said CPU, a dynamic random access memory coupled to said direct memory access controller and to said CPU, and a system control chip coupled to said CPU having an unclocked sleep mode and an unpowered standby mode, the method comprising: receiving in said CPU a command to enter low-power mode; configuring said programmable interrupt controller, using said CPU, to disable acceptance of later interrupts; configuring said direct memory access controller, using said CPU, to disable later direct memory access operations wherein said configuring of said direct memory access controller occurs at a time following said step of configuring said programmable interrupt controller; saving, to said memory, the contents of at least some of said I/O state indicating registers and I/O ports, using said CPU, wherein said saving to said memory access at a time following said step of configuring said direct memory access controller; refreshing said memory, using said CPU, wherein said refreshing of said memory occurs at a time following said step of saving; and initiating said standby mode of said system control chip using said CPU.
Claim 3
Dependent Claim
37 words
A method, as claimed in claim 1, further comprising the steps of: sensing absence of user input for more than a predetermined time, using said CPU; and issuing a command to enter low-power mode, using said CPU.
Claim 4
Dependent Claim
35 words
A method, as claimed in claim 1, further comprising the steps of: sensing a system power level below a predetermined level, using said CPU; and issuing a command to enter low-power mode, using said CPU.
Claim 5
Dependent Claim
33 words
A method, as claimed in claim 1, further comprising the steps of: sensing activation of a user-activatable low-power switch, using said CPU; and issuing a command to enter low-power mode, using said CPU.
Claim 6
Dependent Claim
33 words
A method, as claimed in claim 1, further comprising the steps of: receiving an instruction from a user application, using said CPU; and issuing a command to enter low-power mode, using said CPU.
Claim 7
Dependent Claim
42 words
A method, as claimed in claim 1, wherein said programmable interrupt controller includes an interrupt mask and wherein said step of configuring said programmable interrupt controller comprises: saving said interrupt mask to memory; and setting said interrupt mask to disable later interrupts.
Claim 8
Dependent Claim
37 words
A method, as claimed in claim 1, wherein said step of configuring said direct memory access controller comprises: completing pending direct memory access operations; disabling new direct memory access operations; and disabling the direct memory access controller.
Claim 9
Dependent Claim
32 words
A method, as claimed in claim 1, wherein said data processor further includes a stack and at least a first stack pointer and further comprising saving said stack pointer to said memory.
Claim 10
Dependent Claim
44 words
A method, as claimed in claim 1, wherein said direct memory access controller includes counter registers, a command register, mode registers and page registers and further comprising: saving the contents of said counter registers, command register, mode registers and page registers to said memory.
Claim 11
Dependent Claim
38 words
A method, as claimed in claim 1, wherein said data processor includes a programmable peripheral interface having a plurality of ports, wherein said step of saving comprises saving the contents of said plurality of ports to said memory.
Claim 12
Dependent Claim
34 words
A method, as claimed in claim 1, wherein said data processor includes at least one expanded memory specification port and wherein said step of saving comprises saving the contents of said port to memory.
Claim 13
Dependent Claim
113 words
A method, as claimed in claim 1, wherein said data processor having at least first, second, third, fourth, fifth, sixth, and seventh registers, said first register being a universal asynchronous receiver/transmitter register and having a byte format, said second register being a modem control register, said third register being a line status register, said fourth register being a modem status register, said fifth register being an interrupt enable register, said sixth register being a least significant byte divisor register and said seventh register being a most significant byte divisor register, and wherein said step of saving comprises saving the contents of said first, second, third, fourth, fifth, sixth, and seventh registers to memory.
Claim 14
Dependent Claim
39 words
A method, as claimed in claim 1, wherein said data processor includes parallel port registers including data latch and printer control registers and wherein said step of saving comprises saving the contents of said port registers to said memory.
Claim 15
Dependent Claim
44 words
A method, as claimed in claim 1, wherein said system control chip includes stored indications of DIP switch configurations, a sleep/memory configuration, an EMS configuration port and a non-maskable interrupt control configuration and wherein said step of saving comprises saving said indications to memory.
Claim 16
Dependent Claim
32 words
A method, as claimed in claim 1, wherein said data processor includes an overlay controller including overlay controller flags and wherein said step of saving includes saving said flags to said memory.
Claim 17
Dependent Claim
44 words
A method, as claimed in claim 1, wherein said data processor includes standby mode control logic and wherein said step of initiating said standby mode comprises: enabling said standby mode of said standby mode control logic; and issuing a halt command to said cpu.
Claim 18
Dependent Claim
19 words
A method, as claimed in claim 1, further comprising disabling non-maskable interrupts following said step of receiving a command.
Claim 19
Dependent Claim
41 words
A method, as claimed in claim 1, wherein said memory includes a first program portion and a second portion reserved for use by a basic input/output system, and wherein said step of saving includes saving to said second portion of memory.
Claim 20
Dependent Claim
25 words
A method, as claimed in claim 1, wherein said step of saving comprises saving said contents into fewer than 48 eight-bit bytes of said memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-08-19 | 1995-02-18 | 1995-08-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-08-19 | 1999-02-18 | 1999-08-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-08-19 | 2003-02-18 | 2003-08-20 | $7700.00 | Window Closed / Lapsed |