Data processor system including data-save controller for protection against loss of volatile memory information during power failure

Claim 1

A data processing system comprising: a processor with volatile registers; a data memory; an AC power source; a detector for monitoring said AC power source for failure, and for providing to said processor a first indication of failure when said AC power source falls below a predetermined voltage, a second indication whenever said failure has endured for longer than a first predetermined period, and a third indication of restoration of said AC power whenever said AC power source exceeds said predetermined voltage for longer than a second predetermined period; a power supply receiving energy from said AC power source for delivering power to said system during normal operation, said power supply storing sufficient energy in its internal components to continue to deliver power subsequently to said first indication of failure for said first predetermined period and for a third predetermined period for data transfer; said processor responding to said first indication of failure to perform the following functions constituting a data save operation during said first predetermined period, a data save indication being provided when said functions are successfully completed, said functions including: (a) completion or reinitialization of the current processor task in preparation for recommencement of operation, said reinitialization including returning said volatile registers used for said current processor task to the same state as at the beginning of said current processor task; (b) selecting tasks for recommencement of operation according to priority by checking each task beginning with the highest priority task to ascertain if sufficient time remains to complete the task during said first predetermined period, and performing those tasks able to be completed during said first predetermined period; (c) and upon subsequent receipt of said second indication and during said third predetermined period for data transfer, transfering the contents of said volatile registers to predetermined locations within said data memory, and storing a data save indication in said data memory only when said data save operation is successfully completed, said processor returning to its condition prior to said first indication of failure and resuming said current task if said second indication is not received at the end of said first predetermined period; an energy store responding to the presence of said data save indication for supplying said data memory with power during said failure, said data memory being a volatile memory; and, said processor, upon receipt of said third indication, recovering from said failure by retrieving said contents of said volatile registers from said data memory and restoring them to said volatile registers.