US5117443A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for operating at fractional speeds in synchronous systems
Assignee: PERSONAL COMPUTER SUPPORT GROUP Inc
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Filing: 1989-11-13
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Granted: 1992-05-26
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Expires: 2009-11-13
Abstract
Abstract A synchronous digital system is disclosed which includes a system clock, a first and a second subsystem, each having a clock input, and a circuit for disabling the clock input to the second subsystem on a regular basis. The effective clock rate of the second subsystem is a fraction of the effective clock rate of the first subsystem.
Inventors
- 👤 Glen E. Shires
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 04:25
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0635; H04J3/0685
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
176 words
In a synchronous digital system, a combination including: a clock generator; a first set of registers driven by the clock generator, the registers having both an input for receiving data and an output for transmitting data; a first logic circuit designed to operate at the clock rate, connected in a feedback arrangement from the output of the first set of registers to the input of the first set of registers; a second set of registers driven by the clock generator, the registers having both an input for receiving data and an output for transmitting data; a second logic circuit designed to operate at a predetermined fraction of the clock rate, connected in a feedback arrangement from the output of the second set of registers to the input of the second set of registers; and a circuit for disabling the clock provided for driving the second set of registers on a regular basis wherein the clock provided to the second set of registers which has not been disabled is at the predetermined fraction of the clock rate.
Claim 2
Dependent Claim
176 words
In a synchronous digital system, a combination including: a clock generator; a first set of registers driven by the clock generator, the registers having both an input for receiving data and an output for transmitting data; a first logic circuit designed to operate at the clock rate, connected in a feedback arrangement from the output of the first set of registers to the input of the first set of registers; a second set of registers driven by the clock generator, the registers having both an input for receiving data and an output for transmitting data; a second logic circuit designed to operate at a predetermined fraction of the clock rate, connected in a feedback arrangement from the output of the second set of registers to the input of the second set of registers; and a circuit for disabling the clock provided for driving the second set of registers on a regular basis wherein the clock provided to the second set of registers which has not been disabled is at the predetermined fraction of the clock rate.
Claim 3
Dependent Claim
100 words
A synchronous system comprising in combination: a clock generator; at least two subsystems which are synchronous with each other, each including: (a) a set of registers driven by the clock generator having both inputs for receiving data and outputs for transmitting data; and (b) a flow-through logic circuit that connects the register inputs as some function of the register outputs and possibly other external inputs and outputs; and at least one logic circuit to generate at least one disable signal on a regular basis wherein at least one set of subsystem registers is enabled and disabled on a regular basis.
Claim 4
Dependent Claim
100 words
A synchronous system comprising in combination: a clock generator; at least two subsystems which are synchronous with each other, each including: (a) a set of registers driven by the clock generator having both inputs for receiving data and outputs for transmitting data; and (b) a flow-through logic circuit that connects the register inputs as some function of the register outputs and possibly other external inputs and outputs; and at least one logic circuit to generate at least one disable signal on a regular basis wherein at least one set of subsystem registers is enabled and disabled on a regular basis.
Claim 5
Dependent Claim
66 words
A system according to claim 2 wherein the at least one logic circuit to generate at least one disable signal on a regular basis generates the at least one signal to have the time between a high transition and a low transition be multiple clock pulses such that each of the at least one subsystem is effectively clocked at a fractional rate of the clock generator.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-26 | 1995-11-25 | 1996-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-26 | 1999-11-25 | 2000-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-26 | 2003-11-25 | 2004-05-26 | $7700.00 | Window Closed / Lapsed |