Calculating machines

Claim 2

A calculating machine including transmitting and receiving integrated circuits for transmitting and receiving, between which signal pulses in a plurality of signal channels are passed on a set of interconnecting signal line leads fewer in number than the signal channels, a source of timing pulses, each circuit including a plurality of gates coupled between each lead and a corresponding plurality of signal channels and a plurality of circuit parts connected for transmitting the signals from said channels in a cyclic sequence and for synchronizing the signal pulses between said transmitting and receiving circuits once for each cycle of transmission of signals in response to predetermined timing pulses, at least one of the gates being adapted to be controlled by said predetermined timeing pulses to control the entry of received signals into said receiving integrated circuit.

Claim 3

A calculating machine according to claim 1, wherein the plurality of gates in the pair of integrated circuits includes a plurality of gate circuits which connect a plurality of signal lines to a common signal line between the ''transmit'' integrated circuit and the ''receive'' integrated circuit.

Claim 4

A calculating machine according to claim 2, wherein the plurality of circuit parts compriseing a synchronizing circuit include said source of timing pulses and a counter circuit connected thereto for counting as an endless loop, input circuits for the plurality of gate circuits connected to respective outputs of the counter circuit whereby the oscillator pulses cause the counter circuit to energize the gate circuits in sequence under the control of the predetermined time pulse.

Claim 5

A calculating machine according to claim 3, including a bistable circuit operated by an output of said counter circuit, wherein the predetermined time pulse is generated along a signal channel in the ''transmit'' integrated circuit by the output of said bistable circuit whereby successive predetermined time pulses alternate between one signal level and another signal level.

Claim 6

A calculating machine according to claim 4, including a further bistable circuit operated by an output of said counter circuit and a further pair of gate circuits, wherein the counter circuit of the ''receive'' integrated circuit is controlled by said further bistable circuit and said further pair of gate circuits, means providing one of the further gate circuits an inverted output compared with the output of the other gate circuit, the pair of said further gates having a circuit connecting their outputs to the input of the counter circuit and having an input connected to the common signal line from said transmitting integrated circuit and having another input connected to an output of the further bistable circuit, said circuits comprising means operating if the predetermined time pulse signals are in synchronism so that the signals transmitted along the signal lines of the ''transmit'' integrated circuit are transmitted along the corresponding signal lines of the ''receive'' integrated circuit; and if the predetermined time pulse signals are not in synchronism, the counting operation of the counter circuit of the ''receive'' integrated circuit is stepped under the control of the predetermined time pulse signals until the predetermined signals are in synchronism.

Claim 7

A calculating machine according to claim 5, wherein the counter circuits are registers having a plurality of stages; and wherein the means transmitting the signals in cyclic sequence comprise a plurality of two-input ''and'' logic gates having one input connected to an output of a respective register stage and means connecting the other input to these gates in the ''transmit'' integrated circuit to the respective signal lines and in the ''receive'' integrated circuit to a common signal line between the transmit and receive integrated circuits; and wherein the ''transmit'' integrated circuit includes an ''or'' logic gate whose inputs are connected to respective outputs of the ''and'' LOGIC gates and whose output is connected to the common signal line between said integrated circuits.

Claim 8

A calculating machine according to claim 5 wherein the one gate having an inverted output of the pair of gates comprises an invertor circuit whose input is connected to the common signal line and whose output is connected to an input of the one gate of the pair of gates; and wherein the pair of gates are a pair of ''or'' logic gates whose outputs are connected to the input of the register.

Claim 9

A calculating machine according to claim 7, wherein the first mentioned plurality of gates include a plurality of switch means, each switch means having ''conduction'' connections by which the signal lines are connected to the common signal line and having a ''control'' connection which is connected to an output of the counter circuit, and means operating said switch means whereby when a negative potential is applied to the ''control'' electrode a short circuit exists between the two ''conduction'' electrodes, and when a positive potential is applied to the ''control'' electrodes, an open exists between the two ''conduction'' electrodes.

Claim 10

A calculating machine according to claim 5, wherein the counter circuit with one of the gate circuits having an input connected to the synchronizing circuit comprise a plurality of gate circuits and a plurality of switch means, each of the switch means having ''conduction'' connections by which successive gate circuits are joined together in series to form an endless loop and having ''control'' electrodes in which alternate ''control'' electrodes are connected to the output of the pulse source and in which the remaining ''control'' electrodes are connected to the output of an inverter circuit whose input is connected to the output of the pulse source; and means operating the foregoing whereby a pulse signal is circulated around the counter circuit by the pulses from the pulse source under the control of the synchronizing circuit.

Claim 11

A calculating machine according to claim 5, including switch means with a control connection, wherein the synchronizing means included in the ''transmit'' integrated circuit includes a ''nor'' gate circuit having an input connected to one output of the counter circuit and having the output of the ''nor'' gate circuit connected by a pulse line to the common connection of the signal line through said switch means by ''control'' connection means connected to the output of the counter circuit of the one integrated circuit, a divide-by-two bistable circuit, means connecting another input of the ''nor'' gate circuit to the output of said ''divide-by-two'' bistable circuit, means connecting its input to another output of the counter circuit to operate so that the synchronizing signal from the output of the ''nor'' gate circuit alternates between two voltage magnitudes, when the one output of the counter circuit is successively energized.

Claim 12

A calculating machine according to claim 10, wherein the synchronizing means included in the ''receive'' integrated circuit forms a synchronizing circuit including a ''nand'' gate circuit, a one ''nor'' gate circuit and another ''nor'' gate circuit whose input is connected to the output of the one ''nor'' gate circuit, a circuit including means connecting the outputs of the ''nand'' -gate circuit and the other ''nor'' gate circuit together as the output connection through the ''conduction'' connections of a switch means with a control connection to an input of the counter circuit of the ''receive'' integrated circuit, means connecting the ''control'' connection of the switch means to a first output of the counter circuit in the ''receive'' integrated circuit, which first output corresponds to the first output of the counter circuit in the ''transmit'' integrated circuit, a receive ''divide-by-two'' bistable circuit with an output connected to an input Of both the one ''nor'' gate circuit and the ''nand'' gate circuits, and with the input connected to a second output of the counter circuit which corresponds to the second output of the counter circuit of the other integrated circuit, and means providing whereby, when the synchronizing circuit in the ''receive'' integrated circuit receives the synchronizing pulses from the synchronizing circuit of the ''transmit'' integrated circuit, the synchronizing circuit line of the ''receive'' integrated circuit transmits a signal which depends on whether the logic level of the received synchronizing pulse is the same as the logic level of the bistable circuit output, and providing while the logic levels are the same, that the output connection of the synchronizing circuit allows the counter circuit to operate; and, while the magnitudes are different, the output connection of the synchronizing circuit prevents the counter circuit from operating, the foregoing means providing in the counter circuit of the ''receiver'' integrated circuit a delay in its operation, as a result of the action of its synchronizing circuit, until the counter circuits are in synchronism, when no further delays in operation occur.

Claim 13

A calculating machine according to claim 5, wherein a train of synchronizing pulses, are generated in the synchronizing means in the ''transmit'' integrated circuit during the time that the first counter circuit output in the synchronizing means of the ''receive'' integrated circuit is energized, means transmitting these synchronizing pulses along the signal line to the input of the synchronizing means of the ''receive'' integrated circuit to ensure that the first circuit outputs connected to the synchronizing means of the ''transmit'' and the ''receive'' integrated circuits are energized in synchronism, and, as a result, that the ''receive'' counter circuit outputs also are energized in synchronism.

Claim 14

A calculating machine including means for transmitting a signal from one integrated circuit to another integrated circuit along a single wire comprises a ''transmit'' circuit and a ''receive'' circuit, the ''transmit'' circuit having a ''transmit'' register having a plurality of stages, a gate associated with each stage of the register, means addressing a plurality of signals to these gates, means for applying a train of pulses to the register to apply pulses to the gates in sequence to open said gates in sequence and apply the signals applied to said gates to a single line; and wherein there is included an additional gate and means connecting it to apply a signal to the signal line in alternate of such train of pulses and the ''receive'' circuit having a ''receive'' register having a plurality of stages and gates associated with each stage of the register to which the signals received from the single wire are addressed, a pair of alternately operable input gates to the ''receive'' register and means connected thereto to apply pulses to the ''receive'' register in such a manner that if the signals are in synchronism, the pulses are passed to the receive integrated circuit, but, on receipt of unsynchronous signals, the pulses are delayed until the two trains of pulses are in synchronism.

Claim 15

A calculating machine including means for transmitting a signal from one integrated circuit to another integrated circuit along a single wire comprises a ''transmit'' circuit and a ''receive'' circuit, the ''transmit'' circuit having a ''transmit'' register having a plurality of stages, a gate associated with each stage of the register, means addressing a plurality of signals to these gates, means for applying a train of pulses to the register to apply pulses to the gates in sequence to open said gates in sequence and apply the signals applied to said gates to a single line; and wherein there is included an additional gate and means connecting it to apply a signal to the signal line in alternate of such train of pulses and the ''receive'' circuit having a ''receive'' register having a plurality of stages and gates associated with each stage of the register to which the signals received from the single wire are addressed, a pair of alternately operable input gates to the ''receive'' register and means connected thereto to apply pulses to the ''receive'' register in such a manner that if the signals are in synchronism, the pulses are passed to the receive integrated circuit, but, on receipt of unsynchronous signals, the pulses are delayed until the two trains of pulses are in synchronism.

Claim 16

A calculating machine including two integrated circuits which are connected to a source of oscillator pulses and which are connected together by a signal line for the transmission of signal pulses therebetween, each integrated circuit having plurality of pulse lines each of which has means connecting a respective point on the integrated circuit to a common connection of the signal line through a respective switch means having a ''control'' connection, a counter circuit having a plurality of outputs each of which is connected to a ''control'' connection of a respective one of said switch means, and means for synchronizing the outputs of the counter circuit in the integrated circuit with the outputs of the counter cIrcuit in the other integrated circuit operating in such a manner that the synchronizing means causes the outputs of the counter circuits to be energized in a synchronized sequence so that the said switch means in the respective integrated circuits are sequentially energized to connect in sequence the pulse lines in the respective integrated circuits to the signal line.

Claim 17

A calculating machine including two integrated circuits which are connected to a source of oscillator pulses and which are connected together by a signal line for the transmission of signal pulses therebetween, each integrated circuit having plurality of pulse lines each of which has means connecting a respective point on the integrated circuit to a common connection of the signal line through a respective switch means having a ''control'' connection, a counter circuit having a plurality of outputs each of which is connected to a ''control'' connection of a respective one of said switch means, and means for synchronizing the outputs of the counter circuit in the integrated circuit with the outputs of the counter cIrcuit in the other integrated circuit operating in such a manner that the synchronizing means causes the outputs of the counter circuits to be energized in a synchronized sequence so that the said switch means in the respective integrated circuits are sequentially energized to connect in sequence the pulse lines in the respective integrated circuits to the signal line.