Computer system with a sleep mode function

Claim 2

A computer system with a sleep mode function, comprising: processor means (10), constituting a central pro­cessing unit for said system, for executing various types of data processing; clock control means (18) for selecting one of a first clock pulse of a predetermined high frequency necessary in normal mode of said processor means (10) and a second clock pulse of a predetermined low fre­quency necessary in sleep mode of said processor means (10), and supplying said selected clock pulse to said processor means (10); and sleep mode control means (16) for determining whether or not a predetermined condition for executing said sleep mode is met and controlling said clock control means (18) to supply said second clock pulse to said processor means (10) when said predetermined condition is met; characterized by further comprising: sleep operation control means (16, 17) for per­mitting or inhibiting a control operation of said sleep mode control means (16) and allowing said clock control means (18) to supply said first clock pulse to said processor means (10) upon inhibition of said control operation.

Claim 3

A computer system according to claim 1, charac­terized in that said clock control means (18) has clock generating means (40) for generating said first and second clock pulses, and clock switching means (42) for selecting one of said first and second clock pulses and supplying said selected clock pulse to said processor means (10) under a control of said sleep mode control means (16).

Claim 4

A computer system according to claim 1, charac­terized in that said sleep mode control means (16) has a logic circuit (20b) for outputting a control signal to said clock control means (18) to switch said first clock pulse to said second clock pulse when said condition for setting said sleep mode is satisfied.

Claim 5

A computer system according to claim 1, characterized in that said sleep operation control means (16, 17) has memory means (17) for storing mode control data indicating inhibition of said control operation of said sleep mode control means (16).

Claim 6

A computer system according to claim 3, charac­terized in that said logic circuit (20b) has a logic gate circuit for inhibiting said control signal from being output under a control of said sleep operation control means (16, 17), when said control operation of said sleep mode control means (16) is inhibited.

Claim 7

A computer system with a sleep mode function, comprising: processor means (10), constituting a central pro­cessing unit for said system, for executing various types of data processing; clock control means (18) for selecting one of a first clock pulse of a predetermined high frequency necessary in normal mode of said processor means (10) and a second clock pulse of a predetermined low fre­quency necessary in sleep mode of said processor means (10), and supplying said selected clock pulse to said processor means (10); and sleep mode control means (16) for determining whether or not a predetermined condition for executing said sleep mode is met and controlling said clock control means (18) to supply said second clock pulse to said processor means (10) when said predetermined condition is met; characterized by further comprising: sleep operation control means (16, 17), having memory means (17) for storing mode control data indi­cating permission or inhibition of a control operation of said sleep mode control means (16), for supplying said first clock pulse to said processor means (10) based on said mode control data indicating inhibition of said control operation upon inhibition of said control operation.

Claim 8

A computer system with a sleep mode function, comprising: processor means (10), constituting a central pro­cessing unit for said system, for executing various types of data processing; clock control means (18) for selecting one of a first clock pulse of a predetermined high frequency necessary in normal mode of said processor means (10) and a second clock pulse of a predetermined low fre­quency necessary in sleep mode of said processor means (10), and supplying said selected clock pulse to said processor means (10); and sleep mode control means (16) for determining whether or not a predetermined condition for executing said sleep mode is met and controlling said clock control means (18) to supply said second clock pulse to said processor means (10) when said predetermined condition is met; characterized by further comprising: sleep operation control means (16, 17), having memory means (17) for storing mode control data indi­cating permission or inhibition of a control operation of said sleep mode control means (16), for supplying said first clock pulse to said processor means (10) based on said mode control data indicating inhibition of said control operation upon inhibition of said control operation.

Claim 9

A computer system according to claim 6, charac­terized in that said clock control means (18) has clock generating means (40) for generating said first and second clock pulses, and clock switching means (42) for selecting one of said first and second clock pulses and supplying said selected clock pulse to said processor means (10) under a control of said sleep mode control means (16).

Claim 10

A computer system according to claim 6, charac­terized in that said sleep mode control means (16) has a logic circuit (26b) for outputting a control signal to said clock control means (18) to switch said first clock pulse to said second clock pulse when said condition for setting said sleep mode is satisfied.

Claim 11

A computer system according to claim 8, charac­terized in that said logic circuit (20b) has a logic gate circuit for inhibiting said control signal from being output based on said mode control data stored in said memory means (17) when said control operation of said sleep mode control means (16) is inhibited.

Claim 12

A computer system with a sleep mode function comprising: clock generating means (40) for generating a first clock having a first frequency and a second clock having a second frequency lower than said first frequency; determining means (16) for determining whether or not a predetermined condition for executing a sleep mode is met and instructing to execute the sleep mode when the condition is met; means (18) for switching a first clock output from said clock generating means (40) to a second clock when said determining means instructs execution of the sleep mode; setting means (10) for setting permission/­inhibition of execution of the sleep mode; and control means (17) for inhibiting an instruction of execution of the sleep mode by said determining means (16) when said setting means (10) sets an inhibition of execution of the sleep mode.

Claim 13

A computer system with a sleep mode function comprising: clock generating means (40) for generating a first clock having a first frequency and a second clock having a second frequency lower than said first frequency; determining means (16) for determining whether or not a predetermined condition for executing a sleep mode is met and instructing to execute the sleep mode when the condition is met; means (18) for switching a first clock output from said clock generating means (40) to a second clock when said determining means instructs execution of the sleep mode; setting means (10) for setting permission/­inhibition of execution of the sleep mode; and control means (17) for inhibiting an instruction of execution of the sleep mode by said determining means (16) when said setting means (10) sets an inhibition of execution of the sleep mode.