Patent US6788029B1 successfully refreshed from Google Patents.
US5862373A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pad cells for a 2/N mode clocking scheme
Assignee: Intel Corp
•
Filing: 1996-09-06
•
Granted: 1999-01-19
•
Expires: 2016-09-06
Abstract
Abstract A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
Inventors
- 👤 Chakrapani Pathikonda
- 👤 Jeff Wight
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:09
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
150 words
An integrated circuit for use in a computer system having a bus transferring information using a bus clock signal having a frequency, said integrated circuit comprising: a plurality of pins; a core operable in response to a core clock signal that is a N/2 times the frequency of the bus clock signal, wherein every other phase of the bus clock signal is out of phase with the core clock signal; a plurality of pad cells coupling the plurality of pins to the core, wherein each pad cell comprises an input path having first and second latches coupled in series from a pin to the core and an output path having third and fourth latches coupled in series from the pin to the core, wherein the third latch is clocked by the bus clock signal and the second and fourth latches are clocked by first and second core clock signals respectively.
Claim 2
Dependent Claim
150 words
An integrated circuit for use in a computer system having a bus transferring information using a bus clock signal having a frequency, said integrated circuit comprising: a plurality of pins; a core operable in response to a core clock signal that is a N/2 times the frequency of the bus clock signal, wherein every other phase of the bus clock signal is out of phase with the core clock signal; a plurality of pad cells coupling the plurality of pins to the core, wherein each pad cell comprises an input path having first and second latches coupled in series from a pin to the core and an output path having third and fourth latches coupled in series from the pin to the core, wherein the third latch is clocked by the bus clock signal and the second and fourth latches are clocked by first and second core clock signals respectively.
Claim 3
Dependent Claim
18 words
The integrated circuit defined in claim 1 wherein the first latch is clocked by the bus clock signal.
Claim 4
Dependent Claim
15 words
The integrated circuit defined in claim 1 wherein the first latch comprises a pulsed latch.
Claim 5
Dependent Claim
18 words
The integrated circuit defined in claim 3 wherein the pulsed latch is clocked by a system clock signal.
Claim 6
Dependent Claim
15 words
The integrated circuit defined in claim 1 wherein the third latch comprises a master/slave flip-flop.
Claim 7
Dependent Claim
37 words
The integrated circuit defined in claim 1 wherein the second latch latches information on a high phase of the core clock signal, and the fourth latch latches information on a low phase of the core clock signal.
Claim 8
Dependent Claim
16 words
The integrated circuit defined in claim 1 wherein N is an odd integer greater than two.
Claim 9
Dependent Claim
24 words
The integrated circuit defined in claim 1 wherein the input path further comprises a sense amp coupled between the pin and the first latch.
Claim 10
Dependent Claim
23 words
The integrated circuit defined in claim 1 wherein the input path further comprises a buffer coupled between the pin and the first latch.
Claim 11
Dependent Claim
30 words
The integrated circuit defined in claim 1 further comprising control logic to control the core clock signal to the second latch to prevent relatching of information between core clock cycles.
Claim 12
Dependent Claim
34 words
The integrated circuit defined in claim 1 wherein the second and fourth latches hold data for one half of a core clock cycle in order to transfer the data to an appropriate clock domain.
Claim 13
Dependent Claim
20 words
The integrated circuit defined in claim 1 wherein the first and second core clock signals comprise a single clock signal.
Claim 14
Dependent Claim
25 words
The integrated circuit defined in claim 1 wherein the first and second core clock signals are separately distributed to the input and output paths respectively.
Claim 15
Dependent Claim
21 words
The integrated circuit defined in claim 1 wherein the second and fourth latches remain open when N is an even integer.
Claim 16
Dependent Claim
177 words
An integrated circuit for use in a computer system having a bus transferring information using a bus clock signal having a frequency, said integrated circuit comprising: a plurality of pins; a core operable in response to a core clock signal that is a N/2 times the frequency of the bus clock signal, wherein every other phase of the bus clock signal is out of phase with the core clock signal when N is an odd integer greater than two; a plurality of pad cells means coupling the plurality of pins to the core, wherein each pad cell comprises an input path means having first and second latching means for transferring information from one of the plurality of pins to the core and an output path means having third and fourth latching means for transferring information from the core to said one of the plurality of pins, wherein the third latching means is clocked by the bus clock signal and the second latching means and the fourth latching means are clocked by first and second core clock signals.
Claim 17
Dependent Claim
177 words
An integrated circuit for use in a computer system having a bus transferring information using a bus clock signal having a frequency, said integrated circuit comprising: a plurality of pins; a core operable in response to a core clock signal that is a N/2 times the frequency of the bus clock signal, wherein every other phase of the bus clock signal is out of phase with the core clock signal when N is an odd integer greater than two; a plurality of pad cells means coupling the plurality of pins to the core, wherein each pad cell comprises an input path means having first and second latching means for transferring information from one of the plurality of pins to the core and an output path means having third and fourth latching means for transferring information from the core to said one of the plurality of pins, wherein the third latching means is clocked by the bus clock signal and the second latching means and the fourth latching means are clocked by first and second core clock signals.
Claim 18
Dependent Claim
16 words
The integrated circuit defined in claim 15 wherein the first latching means comprise a pulsed latch.
Claim 19
Dependent Claim
18 words
The integrated circuit defined in claim 16 wherein the pulsed latch is clocked by a system clock signal.
Claim 20
Dependent Claim
16 words
The integrated circuit defined in claim 15 wherein the third latching means comprises a master/slave flip-flop.
Claim 21
Dependent Claim
39 words
The integrated circuit defined in claim 15 wherein the second latching means latches information on a high phase of the core clock signal, and the fourth latching means latches information on a low phase of the core clock signal.
Claim 22
Dependent Claim
34 words
The integrated circuit defined in claim 15 wherein the second and fourth latches hold data for one half of a core clock cycle in order to transfer the data to an appropriate clock domain.
Claim 23
Dependent Claim
20 words
The integrated circuit defined in claim 15 wherein the first and second core clock signals comprise a single clock signal.
Claim 24
Dependent Claim
25 words
The integrated circuit defined in claim 15 wherein the first and second core clock signals are separately distributed to the input and output paths respectively.
Claim 25
Dependent Claim
22 words
The integrated circuit defined in claim 15 wherein the second and fourth latching means remain open when N is an even integer.
References Cited (Backward Citations)
US3096338A
Cited
US3623017A
Cited
US4896260A
Cited
US3715729A
Cited
US3919695A
Cited
US3895311A
Cited
US3931585A
Cited
US3936762A
Cited
US4095267A
Cited
US4639864A
Cited
US4077016A
Cited
US4143418A
Cited
US4264863A
Cited
GB2010551A
Cited
US4203153A
Cited
US4300019A
Cited
US4365290A
Cited
US4758945A
Cited
US4293927A
Cited
US4419756A
Cited
US4405898A
Cited
US4479191A
Cited
US4615005A
Cited
US4438490A
Cited
US4493971A
Cited
EP0103755A2
Cited
US4667289A
Cited
GB2130765A
Cited
US4841440A
Cited
US4698748A
Cited
EP0140814A2
Cited
US4780843A
Cited
US4766567A
Cited
US4881364A
Cited
US4779083A
Cited
US4780836A
Cited
US4669099A
Cited
EP0242010A1
Cited
US4823292A
Cited
US5125088A
Cited
US5083266A
Cited
US4935863A
Cited
US4907183A
Cited
US4814591A
Cited
US4967895A
Cited
US4881205A
Cited
US5133064A
Cited
US4979097A
Cited
US4922450A
Cited
US5305452A
Cited
US4979190A
Cited
US4881165A
Cited
US5129091A
Cited
US5349544A
Cited
US4931748A
Cited
US5025387A
Cited
EP0366250A1
Cited
US4980836A
Cited
US5059924A
Cited
EP0368144A2
Cited
US5175845A
Cited
US5249298A
Cited
EP0375794A1
Cited
EP0385567A2
Cited
US5041962A
Cited
US5319771A
Cited
US5123107A
Cited
US5003537A
Cited
US5021679A
Cited
US4991129A
Cited
US5167024A
Cited
US5235698A
Cited
EP0419908A2
Cited
US5151992A
Cited
US5191657A
Cited
US5117443A
Cited
US5388250A
Cited
US5276824A
Cited
US5077686A
Cited
US5103114A
Cited
EP0451661B1
Cited
US5263172A
Cited
US5251320A
Cited
EP0478132A1
Cited
US5175853A
Cited
US5220672A
Cited
US5239652A
Cited
US5381542A
Cited
US5426755A
Cited
US5239631A
Cited
US5319772A
Cited
US5359232A
Cited
US5336939A
Cited
US5371880A
Cited
US5359630A
Cited
US5355562A
Cited
US5256994A
Cited
US5287384A
Cited
US5392437A
Cited
US5345109A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-18 | 2002-07-20 | 2003-01-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-18 | 2006-07-20 | 2007-01-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-18 | 2010-07-20 | 2011-01-19 | $7700.00 | Window Closed / Lapsed |