Self-timing random access memory

Claim 2

A memory for accessing binary data stored therein during a read operation and for maintaining stored binary data therein during an idle operation, said memory comprising: an array of memory cells, each of which is adapted for storing therein a binary digit; means for initiating a read operation; means responsive to said initiating means, for addressing a memory cell in said array; means for sensing the binary digit stored in the addressed memory cell; means, responsive to said sensing means, for detecting that said binary digit has been sensed; and means, responsive to said detecting means, for terminating a read operation and for initiating an idle operation, to thereby provide a self-timing memory; wherein said sensing means comprises a plurality of sensing circuits, a respective one of which is adapted for sensing the binary digit stored in a respective at least one memory cell in said array; wherein said detecting means comprises means, responsive to said plurality of sensing circuits, for detecting that one of said sensing circuits has sensed a binary digit; and wherein each of said sensing circuits comprises a Differential Latching Inverter (DLI).

Claim 3

The memory of claim 1 wherein said means for initiating a read operation comprises address change detecting means, for initiating a read operation in response to a changed address input to said memory.

Claim 4

The memory of claim 1 wherein said means for initiating a read operation comprises chip select detecting means, for initiating a read operation in response to a chip select signal to said memory.

Claim 5

A memory for accessing binary data stored therein during a read operation and for maintaining stored binary data therein during an idle operation, said memory comprising: an array of memory cells, each of which is adapted for storing therein a binary digit; means for initiating a read operation; means, responsive to said initiating means, for addressing a memory cell in said array; means for sensing the binary digit stored in the addressed memory cell; means, responsive to said sensing means, for detecting that said binary digit has been sensed; and means, responsive to said detecting means, for terminating a read operation and for initiating an idle operation, to thereby provide a self-timing memory; wherein said sensing means comprises a plurality of sensing circuits, a respective one of which is adapted for sensing the binary digit stored in a respective at least one memory cell in said array; wherein said detecting means comprises means, responsive to said plurality of sensing circuits, for detecting that one of said sensing circuits has sensed a binary digit; and wherein said terminating means comprises means for resetting said plurality of sensing circuits.

Claim 6

A memory for accessing binary data stored therein during a read operation and for maintaining stored binary data therein during an idle operation, said memory comprising: an array of memory cells, each of which is adapted for storing therein a binary digit; means for initiating a read operation; means, responsive to said initiating means, for addressing a memory cell in said array; means for sensing the binary digit stored in the addressed memory cell; means, responsive to said sensing means, for detecting that said binary digit has been sensed; and means, responsive to said detecting means, for terminating a read operation and for initiating an idle operation, to thereby provide a self-timing memory; wherein said sensing means comprises a plurality of sensing circuits, a respective one of which is adapted for sensing the binary digit stored in a respective at least one memory cell in said array; wherein said detecting means comprises means, responsive to said plurality of sensing circuits, for detecting that one of said sensing circuits has sensed a binary digit; and wherein said terminating means comprises means for resetting said plurality of sensing circuits.

Claim 7

A memory for accessing binary data stored therein during a read operation and for maintaining stored binary data therein during an idle operation, said memory comprising: an array of memory cells, each of which is adapted for storing therein a binary digit; means for initiating a read operation; means, responsive to said initiating means, for addressing a memory cell in said array; means for sensing the binary digit stored in the addressed memory cell; means, responsive to said sensing means, for detecting that said binary digit has been sensed; and means, responsive to said detecting means, for terminating a read operation and for initiating an idle operation, to thereby provide a self-timing memory; wherein said sensing means comprises a plurality of sensing circuits, a respective one of which is adapted for sensing the binary digit stored in a respective at least one memory cell in said array; wherein said detecting means comprises means, responsive to said plurality of sensing circuits, for detecting that one of said sensing circuits has sensed a binary digit; and wherein said detecting means comprises an OR gate network having a plurality of inputs, a respective input of which is connected to a respective one of said sensing circuits.

Claim 8

A memory for accessing binary data stored therein during a read operation and for maintaining stored binary data therein during an idle operation, said memory comprising: an array of memory cells, each of which is adapted for storing therein a binary digit; means for initiating a read operation; means, responsive to said initiating means, for addressing a memory cell in said array; means for sensing the binary digit stored in the addressed memory cell; means, responsive to said sensing means, for detecting that said binary digit has been sensed; and means, responsive to said detecting means, for terminating a read operation and for initiating an idle operation, to thereby provide a self-timing memory; wherein said sensing means comprises a plurality of sensing circuits, a respective one of which is adapted for sensing the binary digit stored in a respective at least one memory cell in said array; wherein said detecting means comprises means, responsive to said plurality of sensing circuits, for detecting that one of said sensing circuits has sensed a binary digit; and wherein said detecting means comprises an OR gate network having a plurality of inputs, a respective input of which is connected to a respective one of said sensing circuits.

Claim 9

A Random Access Memory (RAM) for storing therein binary data during a write operation, for accessing binary data stored therein during a read operation and for maintaining stored binary data therein during an idle operation, said RAM comprising: an array of RAM cells, each of which is adapted for storing therein a binary digit; means for initiating one of a read operation and a write operation; means, responsive to said initiating means, for addressing a RAM cell in said array; means for storing a binary digit in the addressed RAM cell during a write operation, and for sensing the binary digit stored in the addressed RAM cell during a read operation and during a write operation; means, responsive to said sensing means, for detecting that said binary digit has been sensed; and means, responsive to said detecting means, for terminating a read operation and a write operation and for initiating an idle operation, to thereby provide a self-timing RAM; wherein said sensing means comprises a plurality of sensing circuits, a respective one of which is adapted for sensing the binary digit stored in a respective at least one RAM cell in said array; wherein said detecting means comprises means, responsive to said plurality of sensing circuits, for detecting that one of said sensing circuits has sensed a binary digit; and wherein each of said sensing circuits comprises a Differential Latching Inverter (DLI).

Claim 10

A Random Access Memory (RAM) for storing therein binary data during a write operation, for accessing binary data stored therein during a read operation and for maintaining stored binary data therein during an idle operation, said RAM comprising: an array of RAM cells, each of which is adapted for storing therein a binary digit; means for initiating one of a read operation and a write operation; means, responsive to said initiating means, for addressing a RAM cell in said array; means for storing a binary digit in the addressed RAM cell during a write operation, and for sensing the binary digit stored in the addressed RAM cell during a read operation and during a write operation; means, responsive to said sensing means, for detecting that said binary digit has been sensed; and means, responsive to said detecting means, for terminating a read operation and a write operation and for initiating an idle operation, to thereby provide a self-timing RAM; wherein said sensing means comprises a plurality of sensing circuits, a respective one of which is adapted for sensing the binary digit stored in a respective at least one RAM cell in said array; wherein said detecting means comprises means, responsive to said plurality of sensing circuits, for detecting that one of said sensing circuits has sensed a binary digit; and wherein each of said sensing circuits comprises a Differential Latching Inverter (DLI).

Claim 11

The RAM of claim 6 wherein said means for initiating one of a read operation and a write operation comprises address change detecting means, for initiating one of a read operation and a write operation in response to a changed address input to said RAM.

Claim 12

The RAM of claim 6 wherein said means for initiating a read operation and a write operation comprises chip select detecting means, for initiating one of a read operation and a write operation in response to a chip select signal to said RAM.

Claim 13

The RAM of claim 6 wherein said means for initiating one of a read operation and a write operation comprises write enable detecting means, for initiating a write operation in response to a write enable signal to said RAM.

Claim 14

A Random Access Memory (RAM) for storing therein binary data during a write operation, for accessing binary data stored therein during a read operation and for maintaining stored binary data therein during an idle operation, said RAM comprising: an array of RAM cells, each of which is adapted for storing therein a binary digit; means for initiating one of a read operation and a write operation; means, responsive to said initiating means, for addressing a RAM cell in said array; means for storing a binary digit in the addressed RAM cell during a write operation, and for sensing the binary digit stored in the addressed RAM cell during a read operation and during a write operation; means, responsive to said sensing means, for detecting that said binary digit has been sensed; and means, responsive to said detecting means, for terminating a read operation and a write operation and for initiating an idle operation, to thereby provide a self-timing RAM; wherein said sensing means comprises a plurality of sensing circuits, a respective one of which is adapted for sensing the binary digit stored in a respective at least one RAM cell in said array; wherein said detecting means comprises means, responsive to said plurality of sensing circuits, for detecting that one of said sensing circuits has sensed a binary digit; and wherein said terminating means comprises means for resetting said plurality of sensing circuits.

Claim 15

A Random Access Memory (RAM) for storing therein binary data during a write operation, for accessing binary data stored therein during a read operation and for maintaining stored binary data therein during an idle operation, said RAM comprising: an array of RAM cells, each of which is adapted for storing therein a binary digit; means for initiating one of a read operation and a write operation; means, responsive to said initiating means, for addressing a RAM cell in said array; means for storing a binary digit in the addressed RAM cell during a write operation, and for sensing the binary digit stored in the addressed RAM cell during a read operation and during a write operation; means, responsive to said sensing means, for detecting that said binary digit has been sensed; and means, responsive to said detecting means, for terminating a read operation and a write operation and for initiating an idle operation, to thereby provide a self-timing RAM; wherein said sensing means comprises a plurality of sensing circuits, a respective one of which is adapted for sensing the binary digit stored in a respective at least one RAM cell in said array; wherein said detecting means comprises means, responsive to said plurality of sensing circuits, for detecting that one of said sensing circuits has sensed a binary digit; and wherein said terminating means comprises means for resetting said plurality of sensing circuits.

Claim 16

A Random Access Memory (RAM) for storing therein binary data during a write operation, for accessing binary data stored therein during a read operation and for maintaining stored binary data therein during an idle operation, said RAM comprising: an array of RAM cells, each of which is adapted for storing therein a binary digit; means for initiating one of a read operation and a write operation; means, responsive to said initiating means, for addressing a RAM cell in said array; means for storing a binary digit in the addressed RAM cell during a write operation, and for sensing the binary digit stored in the addressed RAM cell during a read operation and during a write operation; means, responsive to said sensing means, for detecting that said binary digit has been sensed; and means, responsive to said detecting means, for terminating a read operation and a write operation and for initiating an idle operation, to thereby provide a self-timing RAM; wherein said sensing means comprises a plurality of sensing circuits, a respective one of which is adapted for sensing the binary digit stored in a respective at least one RAM cell in said array; wherein said detecting means comprises means, responsive to said plurality of sensing circuits, for detecting that one of said sensing circuits has sensed a binary digit; and wherein said detecting means comprises an OR gate network having said plurality of inputs, a respective input of which is connected to a respective one of said sensing circuits.

Claim 17

A Random Access Memory (RAM) for storing therein binary data during a write operation, for accessing binary data stored therein during a read operation and for maintaining stored binary data therein during an idle operation, said RAM comprising: an array of RAM cells, each of which is adapted for storing therein a binary digit; means for initiating one of a read operation and a write operation; means, responsive to said initiating means, for addressing a RAM cell in said array; means for storing a binary digit in the addressed RAM cell during a write operation, and for sensing the binary digit stored in the addressed RAM cell during a read operation and during a write operation; means, responsive to said sensing means, for detecting that said binary digit has been sensed; and means, responsive to said detecting means, for terminating a read operation and a write operation and for initiating an idle operation, to thereby provide a self-timing RAM; wherein said sensing means comprises a plurality of sensing circuits, a respective one of which is adapted for sensing the binary digit stored in a respective at least one RAM cell in said array; wherein said detecting means comprises means, responsive to said plurality of sensing circuits, for detecting that one of said sensing circuits has sensed a binary digit; and wherein said detecting means comprises an OR gate network having said plurality of inputs, a respective input of which is connected to a respective one of said sensing circuits.