Memory circuit with active load

Claim 1

A memory circuit comprising: a data input terminal, a data output terminal, a reference voltage source, a memory matrix including a plurality of memory cells arranged in matrix form, each column of said memory matrix including a bit line and an inverted-bit line connected to corresponding memory cells in the column, a data line driving circuit including: a data line and an inverted data line connected to said bit line and inverted-bit line, respectively, in each column, an active load circuit including two MOS transistors operating in their triode regions while regions while a write enable signal is applied, each of said two MOS transistors being connected between said reference voltage source and one of said data line and said inverted data line, whereby said two MOS transistors operate as resistive elements; an inverted write enable signal input terminal, a sense amplifier circuit including a differential amplifier having a pair of input transistors in differential configuration with input terminals respectively coupled to said data line and said inverted data line, an output electrode of at least one of said input transistors being connected to said data output terminal, a plurality of constant current sources connected in parallel between a junction of said pair of input transistors and a reference potential, one of said plurality of constant current sources including switching means controlled by the inverted write enable signal so as to be nonconductive during a write operation, at least one of said current sources being conductive during reading and writing.