US4379344A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Precharge circuit
Assignee: NEC Corp
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Filing: 1981-02-17
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Granted: 1983-04-05
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Expires: 2001-02-17
Abstract
Abstract A precharge circuit having improved equalizing function and suitable for a high-speed digital circuit is disclosed. The circuit comprises a pair of precharge nodes, an equalizer insulated gate field effect transistor connected between said nodes and means for operatively supplying a gate of the equalizer transistor with a voltager larger than a power supply voltage thereby to operate the equalizer transistor in a triode region.
Inventors
- 👤 Takashi Ozawa
- 👤 Yasuhiko Nagahashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 01:27
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
114 words
A circuit comprising a first and a second nodes, a power supply terminal receiving a power voltage, a first and a second insulated gate field effect transistors connected between said first and second nodes and said power supply terminal respectively, a third insulated gate field effect transistor connected between said first and second nodes, first control means for generating a first control signal, means for supplying said first control signal to gates of said first and second transistors, second control means for generating a second control signal having a voltage value larger than said power voltage in absolute value, and means for supplying said second control signal to a gate of said third transistor.
Claim 2
Dependent Claim
114 words
A circuit comprising a first and a second nodes, a power supply terminal receiving a power voltage, a first and a second insulated gate field effect transistors connected between said first and second nodes and said power supply terminal respectively, a third insulated gate field effect transistor connected between said first and second nodes, first control means for generating a first control signal, means for supplying said first control signal to gates of said first and second transistors, second control means for generating a second control signal having a voltage value larger than said power voltage in absolute value, and means for supplying said second control signal to a gate of said third transistor.
Claim 3
Dependent Claim
28 words
The circuit according to claim 1, in which said second control signal is larger than said power voltage by at least a threshold voltage of said third transistor.
Claim 4
Dependent Claim
22 words
The circuit according to claim 1, further comprising data means for operatively generating a voltage difference between said first and second nodes.
Claim 5
Dependent Claim
22 words
The circuit according to claim 1, in which said second control signal is activated before an activation of said first control signal.
Claim 6
Dependent Claim
16 words
The circuit according to claim 1, in which said first control signal takes said power voltage.
Claim 7
Dependent Claim
117 words
In a circuit including a first and a second data nodes, a voltage source of a first voltage, a first insulated gate field effect transistor coupled between said first node and said voltage source, a second insulated gate field effect transistor coupled between said second node and said voltage source, and a third insulated gate field effect transistor connected between said first and second nodes, said first to third transistors being made conductive in a precharge period thereby to precharge said first and second nodes, the improvement comprises means for operatively supplying a gate of said third transistor with a second voltage, an absolute value of said second voltage being larger than that of said first voltage.
Claim 8
Dependent Claim
117 words
In a circuit including a first and a second data nodes, a voltage source of a first voltage, a first insulated gate field effect transistor coupled between said first node and said voltage source, a second insulated gate field effect transistor coupled between said second node and said voltage source, and a third insulated gate field effect transistor connected between said first and second nodes, said first to third transistors being made conductive in a precharge period thereby to precharge said first and second nodes, the improvement comprises means for operatively supplying a gate of said third transistor with a second voltage, an absolute value of said second voltage being larger than that of said first voltage.
Claim 9
Dependent Claim
27 words
The circuit according to claim 6, further comprising means for selectively discharging a charged voltage at either of said first and second node after said precharge period.
Claim 10
Dependent Claim
15 words
The circuit according to claim 6, in which said supplying means includes a boot-strap circuit.
Claim 11
Dependent Claim
44 words
The circuit according to claim 6, further comprising a differential amplifier having a first and a second input terminals, first means for connecting said first input terminal to said first node, and second means for connecting said second input terminal to said second node.
Claim 12
Independent Claim
214 words
A device comprising a plurality of memory cells, a plurality of word lines, a plurality of digit line pairs, each of said digit line pairs including a first and a second digit lines, a plurality of sense amplifiers provided for each of said digit line pairs, each of said sense amplifiers including a first input terminal receivable a signal from said first digit line and a second input terminal receivable a signal from said second digit line, a voltage terminal for receiving a first voltage, a plurality of first insulated gate field effect transistor connected between said voltage terminal and said first digit line, a plurality of second insulated gate field effect transistor connected between said voltage terminal and said second digit lines, a plurality of third insulated gate field effect transistor connected between said first and second digit line in each of said digit line pairs, first means for operatively generating a first control signal having the substantially same voltage as said first voltage, second means for supplying gates of said first transistors with said first control signal, third means for operatively generating a second control signal having a voltage larger than said first voltage in absolute value, and fourth means for supplying gates of said third transistors with said second control signal.
Claim 13
Independent Claim
214 words
A device comprising a plurality of memory cells, a plurality of word lines, a plurality of digit line pairs, each of said digit line pairs including a first and a second digit lines, a plurality of sense amplifiers provided for each of said digit line pairs, each of said sense amplifiers including a first input terminal receivable a signal from said first digit line and a second input terminal receivable a signal from said second digit line, a voltage terminal for receiving a first voltage, a plurality of first insulated gate field effect transistor connected between said voltage terminal and said first digit line, a plurality of second insulated gate field effect transistor connected between said voltage terminal and said second digit lines, a plurality of third insulated gate field effect transistor connected between said first and second digit line in each of said digit line pairs, first means for operatively generating a first control signal having the substantially same voltage as said first voltage, second means for supplying gates of said first transistors with said first control signal, third means for operatively generating a second control signal having a voltage larger than said first voltage in absolute value, and fourth means for supplying gates of said third transistors with said second control signal.
References Cited (Backward Citations)
US4077031A
Cited
US4099265A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-04-04 | 1986-10-04 | 1987-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-04-04 | 1990-10-04 | 1991-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-04-04 | 1994-10-04 | 1995-04-05 | $7700.00 | Window Closed / Lapsed |