High speed address buffer for semiconductor memory

Claim 2

A memory system of the type having an array of memory cells selectively addressed by row and column signals, said signals being generated from row and column address buffers, said buffers including a plurality of flip-flops, said flip-flops including a pair of cross-coupled transistors having set and reset nodes, said set node being coupled to a first load transistor for charging said set node at a rate proportional to the potential on a set control node, said reset node being coupled to a second load transistor for charging said reset node at a rate proportional to the potential on a reset control node, the improvement comprising: a. equalizing means for equalizing the voltage of said set and reset nodes; b. precharge means for applying a precharge to said set control node and said reset control node; c. means for generating a voltage difference between said set node and said reset node in response to an input address signal; and d. current sinking means for sensing a voltage difference between said set node and said reset node and for selectively sinking said precharge from one of said control nodes in response thereto.

Claim 3

A memory system according to claim 1, wherein all of said transistors are MOS transistors.

Claim 4

A memory system according to claim 2, wherein said current sinking means includes first and second MOS sink transistors; said first sink transistor having a gate coupled to said reset node, and having a source coupled to said set control node; said second sink transistor having a gate coupled to said set node, and having a source coupled to said reset control node.

Claim 5

A memory system according to claim 3, wherein said current sinking means includes third and fourth MOS sink transistors; said third sink transistor having a gate coupled to said reset node and having a source coupled to the drains of said first sink transistor and said set transistor; said fourth sink transistor having a gate coupled to said set node and having a source coupled to the drains of said second sink transistor and said reset transistor.

Claim 6

A memory system according to claim 3, wherein said current sinking means includes third and fourth MOS sink transistors; said third sink transistor having a clocked gate, and a source coupled to the drains of said first sink transistor and said set transistor; said fourth sink transistor having a clocked gate, and a source coupled to the drains of said second sink transistor and said reset transistor.

Claim 7

A memory system according to claim 2, wherein said equalizing means is a transistor having a source and a drain coupled to said set node and said reset node respectively, and having a clocked gate.

Claim 8

A memory system according to claim 2, wherein said precharge means includes first, second, and third percharge transistors; said first precharge transistor having a drain coupled to said set control node; said second precharge transistor having a drain coupled to said reset control node; said third precharge transistor having a source coupled to said set control node, and having a drain coupled to said reset control node; each of said precharge transistors having a clocked gate.

Claim 9

A memory system according to claim 2, wherein said address input means includes a first input transistor having a source coupled to said reset node, and a gate capable of receiving an input logic signal.

Claim 10

A memory system according to claim 2, wherein each of said flip-flops includes an output circuit coupled to said set control node and coupled to said reset control node.

Claim 11

A memory system according to claim 9, wherein said output circuit includes an output load transistor having a gate coupled to said set control node; and an output driver transistor having a gate coupled to said reset control node and having a source coupled to the drain of said output load transistor.

Claim 12

A memory system according to claim 9, wherein said output circuit includes an output load transistor having a gate coupled to said reset control node; and an output driver transistor having a gate coupled to said set control node and having a source coupled to the drain of said output load transistor.

Claim 13

A buffer circuit, for latching logic signals, comprising: a. set and reset transistors being cross-coupled to form set and reset nodes; b. first load transistor means having an output coupled to said set node for charging said set node, and having a set control node for varying the conductivity of said first load transistor in proportion to the charge applied thereto; c. second load transistor means having an output coupled to said reset node for charging said reset node, and having a reset control node for varying the conductivity of said second load transistor in proportion to the charge applied thereto; d. equalizing means for equalizing the voltage on said set and reset nodes; e. precharge means for applying a precharge voltage on said set control node and said reset control node, thereby making each of said load transistors slightly conductive; f. address input means coupled to said reset node for sinking charge from said reset node in response to a first state of an input address signal; and g. current sinking means coupled to said set and reset nodes, and to said set control node and reset control node; said current sinking means selectively sinking charge from said set control node or said reset control node in response to a voltage difference between said set and reset nodes.

Claim 14

A buffer circuit, for latching logic signals, comprising: a. set and reset transistors being cross-coupled to form set and reset nodes; b. first load transistor means having an output coupled to said set node for charging said set node, and having a set control node for varying the conductivity of said first load transistor in proportion to the charge applied thereto; c. second load transistor means having an output coupled to said reset node for charging said reset node, and having a reset control node for varying the conductivity of said second load transistor in proportion to the charge applied thereto; d. equalizing means for equalizing the voltage on said set and reset nodes; e. precharge means for applying a precharge voltage on said set control node and said reset control node, thereby making each of said load transistors slightly conductive; f. address input means coupled to said reset node for sinking charge from said reset node in response to a first state of an input address signal; and g. current sinking means coupled to said set and reset nodes, and to said set control node and reset control node; said current sinking means selectively sinking charge from said set control node or said reset control node in response to a voltage difference between said set and reset nodes.

Claim 15

A buffer circuit according to claim 12, wherein all of said transistors are MOS transistors.

Claim 16

A buffer circuit according to claim 13, wherein said current sinking means includes first and second sink transistors; said first sink transistor having a gate coupled to said reset node, and having a source coupled to said set control node; said second sink transistor having a gate coupled to said set node, and having a source coupled to said reset control node.

Claim 17

A buffer circuit according to claim 13, wherein said current sinking means includes third and fourth sink transistors; said third sink transistor having a gate coupled to said reset node and having a source coupled to the drains of said first sink transistor having a gate coupled to said set node and having a source coupled to the drains of said second sink transistor and said reset transistor.

Claim 18

A buffer circuit according to claim 13, wherein each of said flip-flops includes an output circuit coupled to said set control node and coupled to said reset control node.

Claim 19

A buffer circuit according to claim 16 wherein said output circuit includes an output load transistor having a gate coupled to said set control node; and an output driver transistor having a gate coupled to said reset control node and having a source coupled to the drain of said output load transistor.

Claim 20

A buffer circuit according to claim 16, wherein said output circuit includes an output load transistor having a gate coupled to said reset control node; and an output driver transistor having a gate coupled to said set control node and having a source coupled to the drain of said output load transistor.