Data line potential setting circuit and MIS memory circuit using the same

Claim 2

A data line potential setting circuit comprising: a switching means including a control terminal and first and second output terminals, the first output terminal being connected with one of paired data lines which are receptive of signals of opposite phases, respectively, the second output terminal being connected with the other of said paired data lines; and a control circuit having its output terminal connected with the control terminal of said switching means, whereby the potential difference between said data lines is reduced by rendering said switching means conductive.

Claim 3

A data line potential setting circuit according to claim 1, wherein said switching means is operated in a nonsaturated region.

Claim 4

A data line potential setting circuit according to claim 2, wherein said switching means includes an insulate gate field effect transistor which is rendered conductive by the control signals at a higher level than the threshold voltage of the potentials at the said paired data lines.

Claim 5

A data line potential setting circuit comprising: a first switching means including a control terminal and first and second output terminals, the first output terminal being connected with a reference voltage terminal, the second output terminal being connected with one of paired data lines which are receptive of signals of opposite phases, respectively; second switching means including a control terminal and first and second output terminals, the first output terminal being connected with said reference voltage terminal, the second output terminal being connected with the other of said paired data lines; and a control circuit having its output terminal connected with the control terminals of the first and second switching means, whereby the potentials at said paired data lines are forcibly changed to the voltage at said reference voltage terminal by rendering the first and second switching means conductive.

Claim 6

A data line potential setting circuit comprising: a first switching means including a control terminal and first and second output terminals, the first output terminal being connected with a reference voltage terminal, the second output terminal being connected with one of paired data lines which are receptive of signals of opposite phases, respectively; second switching means including a control terminal and first and second output terminals, the first output terminal being connected with said reference voltage terminal, the second output terminal being connected with the other of said paired data lines; and a control circuit having its output terminal connected with the control terminals of the first and second switching means, whereby the potentials at said paired data lines are forcibly changed to the voltage at said reference voltage terminal by rendering the first and second switching means conductive.

Claim 7

A data line potential setting circuit according to claim 4, further comprising third switching means including a control terminal and first and second output terminals, the first output terminal being connected with one of said paired data lines, the second output terminal being connected with the other of said paired common data lines, said control terminal being connected with the output terminal of said control circuit.

Claim 8

A data line potential setting circuit according to claim 5, wherein the first and second switching means are operated under their saturated conditions whereas the third switching means is operated under its not-saturated condition.

Claim 9

A data line potential setting circuit according to claim 5, the first to third switching means are made of an insulate gate field effect transistors, and wherein the insulate gate field effect transistor making up the third switching means is rendered conductive by the control signals at a higher level than the threshold voltage of the potentials at said paired data lines.

Claim 10

An MIS memory circuit comprising: a plural pairs of digit lines connected commonly with the input and output terminals of a plurality of memory cells, respectively; a pair of common data lines; a gate means for connecting one selected from said plural pairs of digit lines with said pair of common data lines; a write and read out circuits connected with said pair of common data lines; an insulate gate field effect transistor including a gate electrode and first and second output terminals, the first output terminal being connected with one of said pair of common data lines, the second output terminal being connected with the other of said pair of common data lines and a control circuit having its output terminal connected with the gate electrode of said insulate gate field effect transistor, whereby the potential difference between said pair of common data lines is reduced in advance by rendering said insulate gate field effect transistor before the reading operation of the data signals out of said memory cells is started.

Claim 11

An MIS memory circuit comprising: a plural pairs of digit lines connected commonly with the input and output terminals of a plurality of memory cells, respectively; a pair of common data lines; a gate means for connecting one selected from said plural pairs of digit lines with said pair of common data lines; a write and read out circuits connected with said pair of common data lines; an insulate gate field effect transistor including a gate electrode and first and second output terminals, the first output terminal being connected with one of said pair of common data lines, the second output terminal being connected with the other of said pair of common data lines and a control circuit having its output terminal connected with the gate electrode of said insulate gate field effect transistor, whereby the potential difference between said pair of common data lines is reduced in advance by rendering said insulate gate field effect transistor before the reading operation of the data signals out of said memory cells is started.

Claim 12

An MIS memory circuit according to claim 8, wherein said MIS memory circuit is so constructed that it is controlled to a held condition and a stand-by condition by chip selecting signals, and wherein said control circuit is so constructed as to render said insulate gate field effect transistor conductive in response to the chip selecting signals at a level to instruct said held condition.

Claim 13

An MIS memory circuit comprising: a plural pairs of digit lines connected commonly with an input and output terminals of a plurality of a memory cells, respectively; a pair of common data lines; gate means for connecting one selected from said plural pairs of digit lines with said pair of common data lines; a wirte and read out circuits connected with said pair of common data lines; a first insulate gate field effect transistor including a gate electrode and first and second output terminals, the first output terminal being connected with a reference voltage terminal, the second output terminal being connected with one of said pair of common data lines; a second insulate gate field effect transistor including a gate electrode and first and second output terminals, the first output terminal being connected with said reference voltage terminal, the second output terminal being connected with the other of said pair of common data lines; and a control circuit having its output terminal connected with the gate electrodes of the first and second insulate gate field effect transistor, whereby the respective potentials at said pair of common data lines are forcibly changed to the potential at said reference voltage terminal by feeding the control signals at a high level from said control circuit to said gate electrodes before the reading operation of data signals out of said memory cells is started.

Claim 14

An MIS memory circuit comprising: a plural pairs of digit lines connected commonly with an input and output terminals of a plurality of a memory cells, respectively; a pair of common data lines; gate means for connecting one selected from said plural pairs of digit lines with said pair of common data lines; a wirte and read out circuits connected with said pair of common data lines; a first insulate gate field effect transistor including a gate electrode and first and second output terminals, the first output terminal being connected with a reference voltage terminal, the second output terminal being connected with one of said pair of common data lines; a second insulate gate field effect transistor including a gate electrode and first and second output terminals, the first output terminal being connected with said reference voltage terminal, the second output terminal being connected with the other of said pair of common data lines; and a control circuit having its output terminal connected with the gate electrodes of the first and second insulate gate field effect transistor, whereby the respective potentials at said pair of common data lines are forcibly changed to the potential at said reference voltage terminal by feeding the control signals at a high level from said control circuit to said gate electrodes before the reading operation of data signals out of said memory cells is started.

Claim 15

An MIS memory circuit according to claim 10, further comprising a third insulate gate field effect transistor including a gate electrode and first and second output terminals, the first output terminal being connected with one of said pair of common data lines, the second output terminal being connected with the other of said pair of common data lines, said gate electrode being connected with the output terminal of said control circuit.

Claim 16

An MIS memory circuit according to claim 11, wherein said MIS memory circuit is so constructed that it is controlled to a held condition and a stand-by condition by chip selecting signals, and wherein said control circuit is so constructed as to render the first to third insulate gate field effect transistors conductive in response to the chip selecting signals at a level to instruct said held condition.

Claim 17

An MIS memory circuit according to claim 11, wherein the first and second insulate gate field effect transistors are operated in their saturated regions whereas the third insulate gate field effect transistor is operated in its non-saturated region.

Claim 18

An MIS memory circuit according to claim 11, wherein said control circuit is so constructed as to feed the control signals at a higher level than the threshold voltage of the potentials at said pair of common data lines to the gate electrode of the third insulate gate field effect transistor.

Claim 19

An MIS memory circuit according to claim 11, wherein said control circuit is so constructed as to render the first to third insulate gate field effect transistors conductive for a predetermined time after the data signals are written in said memory cells.

Claim 20

An MIS memory circuit according to claim 11, further comprising voltage feed means connected with said pair of common data lines for feeding the middle potential within the potential range of said pair of common data lines, which is varied by said memory cells.

Claim 21

An MIS memory circuit according to claim 16, wherein said voltage feed means includes a fourth and fifth insulate gate field effect transistors connected between a supply terminal and said pair of common data lines and adapted to be rendered inconductive when the data signals are written in said memory cells.