US4612631A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Static type semiconductor memory circuit
Assignee: Toshiba Corp
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Filing: 1984-03-23
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Granted: 1986-09-16
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Expires: 2004-03-23
Abstract
Abstract A static type memory circuit has a plurality of memory cells arranged in a matrix form, a plurality of word lines and a plurality of pairs of bit lines, each of the word lines being coupled to memory cells on a corresponding row, each pair of the bit lines being commonly coupled to memory cells on a corresponding column, a sense amplifier circuit coupled to the bit lines, a row decoder for energizing one of the word lines in response to row address data, a transition detecting circuit for generating an output signal when the row address data is changed, a control signal generator for causing the sense amplifier circuit to be active in response to the output signal from the transition detecting circuit, and a precharge control circuit for controlling precharging of the bit lines in response to the output signal from the transition detecting circuit. The precharge control circuit precharges the bit line to "1" level potential when the sense amplifier circuit is rendered nonoperative in response to the output signal from the control signal generator, and stops the precharging operation in response to an output signal from the transition detecting circuit.
Inventors
- 👤 Kiyofumi Ochii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:28
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
246 words
A semiconductor memory circuit responsive to address data comprising: a plurality of memory cells; a plurality of word lines and bit lines which are connected to said plurality of memory cells to select at least one of said plurality of memory cells; sense amplifier means coupled to said plurality of bit lines; transition detecting means for generating an output signal when said transition detecting means detects that address data has been changed; word line selection means for selecting at least one of said plurality of word lines in response to the address data; control means for supplying a control signal to said sense amplifier means to set said sense amplifier means in an operative mode for a predetermined period of time in response to said output signal from said transition detecting means, thereby to cause the reading of data in a given memory cycle from said at least one selected memory cell onto those of said plurality of bit lines connected to said at least one selected memory cell; data holding means for holding data read out from said at least one selected memory cells through those of said plurality of bit lines connected to said at least one selected memory cell; and potential setting means for setting said bit lines to an initial potential level within said given memory cycle after the data read out from said at least one selected memory cells in the given memory cycle are held in said data holding means.
Claim 2
Dependent Claim
246 words
A semiconductor memory circuit responsive to address data comprising: a plurality of memory cells; a plurality of word lines and bit lines which are connected to said plurality of memory cells to select at least one of said plurality of memory cells; sense amplifier means coupled to said plurality of bit lines; transition detecting means for generating an output signal when said transition detecting means detects that address data has been changed; word line selection means for selecting at least one of said plurality of word lines in response to the address data; control means for supplying a control signal to said sense amplifier means to set said sense amplifier means in an operative mode for a predetermined period of time in response to said output signal from said transition detecting means, thereby to cause the reading of data in a given memory cycle from said at least one selected memory cell onto those of said plurality of bit lines connected to said at least one selected memory cell; data holding means for holding data read out from said at least one selected memory cells through those of said plurality of bit lines connected to said at least one selected memory cell; and potential setting means for setting said bit lines to an initial potential level within said given memory cycle after the data read out from said at least one selected memory cells in the given memory cycle are held in said data holding means.
Claim 3
Dependent Claim
106 words
A circuit according to claim 1, wherein said potential setting means comprises a plurality of switching means each of which has one end coupled to a power supply terminal and another end coupled to corresponding one of said bit lines, and a precharge control circuit for keeping said switching means in a conductive state within a predetermined period of time in response to the output signal from said transition detecting means and the control signal from said sense amplifier control means, said predetermined line beginning after said sense amplifier means is rendered nonoperative and before a next output signal is generated from said transition detecting means.
Claim 4
Dependent Claim
32 words
A circuit according to claim 2, wherein said work line selection means includes means for selecting one of said word lines in response to said output signal from said transition detecting means.
Claim 5
Dependent Claim
48 words
A circuit according to claim 3, wherein said precharge control circuit comprises an RS flip-flop which is set in response to the transition detection signal supplied from said transition detecting means and which is reset in response to the control signal supplied from said sense amplifier control means.
Claim 6
Dependent Claim
70 words
A circuit according to claim 2, wherein said data holding means comprises at least one data line coupled to said bit lines through a switching circuit, a potential setting circuit for setting said at least one data line at a predetermined potential in response to an output signal from said precharge control circuit, and a data holding circuit for holding memory data sent through said at least one data line.
Claim 7
Dependent Claim
14 words
A circuit according to claim 5, wherein said data holding circuit comprises a flip-flop.
Claim 8
Dependent Claim
37 words
A circuit according to claim 5, wherein said data holding circuit comprises a latch for latching data appearing on said at least one data line in response to an output signal from said sense amplifier control means.
Claim 9
Dependent Claim
104 words
A circuit according to claim 1, wherein a pair of bit lines of said plurality of bit lines are coupled to said memory cells of each column; and wherein said potential setting means comprises load resistive means coupled between said pair of bit lines and said power supply terminal, switching means coupled to said pair of bit lines, and a precharge control circuit for keeping said switching means in a conductive state within a predetermined period of time after said transition detecting means and said sense amplifier means are rendered nonoperative and before a next output signal is generated from said transition detecting means.
Claim 10
Dependent Claim
32 words
A circuit according to claim 8, wherein said word line selection means includes means for selecting one of said work lines in response to said output signal from said transition detecting means.
Claim 11
Dependent Claim
48 words
A circuit according to claim 8, wherein said precharge control circuit comprises an RS flip-flop which is set in response to the transition detection signal supplied from said transition detecting means and which is reset in response to the control signal supplied from said sense amplifier control means.
Claim 12
Dependent Claim
32 words
A circuit according to claim 1, wherein said word line selection means includes means for selecting one of said word lines in response to said output signal from said transition detecting means.
References Cited (Backward Citations)
US4417328A
Cited
US4405996A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-09-15 | 1990-03-17 | 1990-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-09-15 | 1994-03-17 | 1994-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-09-15 | 1998-03-17 | 1998-09-16 | $7700.00 | Window Closed / Lapsed |