Charge-transfer sense amplifier for dram and operating method therefor

Claim 2

A charge-transfer sense amplifier receiving complementary signals on a pair of signal lines, comprising a flip-flop type latch circuit with a pair of latching nodes for amplifying a differential signal between said pair of signal lines; a pair of switching elements each having a source-drain connected between a respective one of said pair of signal lines and a corresponding one of said latching nodes of said latch circuit; and precharge elements for precharging said latching nodes to a predetermined first potential, each of said switching elements having a control gate; coupling capacitances respectively connected between the control gate of each element in one line of said pair of signal lines and the other line of said pair of signal lines in a cross-coupled configuration, and means synchronized to the precharging of said latching nodes, for precharging the control gates of said pair of switching elements to a predetermined second potential different from and a value relative to said predetermined first potential sufficient to bring said switching elements into substantially a cut-off state.

Claim 3

The sense amplifier according to claim 1, wherein said pair of signal lines is precharged to a third predetermined potential V different from said first and second potentials at the time of precharging said latching nodes, and said second predetermined potential is at a level of (V+Vth), where threshold voltages of said switching elements are Vth.

Claim 4

The sense amplifier according to claim 2, wherein said pair of signal lines is a pair of bit lines in a dynamic random access memory to which memory cells in one column are connected, and further including means for precharging the pair of bit lines to one-half of an operating supply potential Vcc of said dynamic random access memory.

Claim 5

A dynamic random access memory having a plurality of memory cells arranged in a matrix of rows and columns, a plurality of bit lines each for designating an associated column of said memory cell matrix and arranged such that two bit lines constitute a pair to receive a pair of complementary signals, charge-transfer sense amplifiers provided respectively for said pairs of bit lines, a respective one of said charge-transfer sense amplifiers comprising a flip-flop type latch circuit with a pair of latching nodes for amplifying a differential signal between a corresponding pair of bit lines, a pair of switching elements, each having a source-drain path connected between a respective one of said latching nodes and a corresponding one of said bit lines, each one of said switching elements having a control gate, and precharging elements precharging said latching nodes to a first predetermined potential, each of said charge-transfer sense amplifiers further comprising: coupling capacitances respectively connected between the control gate of each of said switching elements in one line of said pair of bit lines and the other line of said pair of bit lines, in a cross-coupled configuration, and means, synchronized to the precharging of said latching nodes, for precharging the control gates of said pair of switching elements to a second predetermined potential different from and of a value relative to said first predetermined potential sufficient to bring said switching elements in substantially a cut-off state.

Claim 6

A dynamic random access memory having a plurality of memory cells arranged in a matrix of rows and columns, a plurality of bit lines each for designating an associated column of said memory cell matrix and arranged such that two bit lines constitute a pair to receive a pair of complementary signals, charge-transfer sense amplifiers provided respectively for said pairs of bit lines, a respective one of said charge-transfer sense amplifiers comprising a flip-flop type latch circuit with a pair of latching nodes for amplifying a differential signal between a corresponding pair of bit lines, a pair of switching elements, each having a source-drain path connected between a respective one of said latching nodes and a corresponding one of said bit lines, each one of said switching elements having a control gate, and precharging elements precharging said latching nodes to a first predetermined potential, each of said charge-transfer sense amplifiers further comprising: coupling capacitances respectively connected between the control gate of each of said switching elements in one line of said pair of bit lines and the other line of said pair of bit lines, in a cross-coupled configuration, and means, synchronized to the precharging of said latching nodes, for precharging the control gates of said pair of switching elements to a second predetermined potential different from and of a value relative to said first predetermined potential sufficient to bring said switching elements in substantially a cut-off state.

Claim 7

The dynamic random access memory according to claim 4, wherein said plurality of bit lines are precharged to a third potential V, each of said pair of switching elements has a threshold voltage Vth, and said second potential is set at a level of (V+Vth).

Claim 8

The dynamic random access memory according to claim 5, wherein said third potential is one-half of Vcc, where Vcc is an operating supply potential of said dynamic random access memory.