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JPS566541A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor logic circuit

Assignee: NEC Corp
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Filing: 1979-06-28
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Granted: —
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Expires: 1999-06-28
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Abstract

Abstract PURPOSE:To obtain a complementary semicondcutor circuit which can shift freely the logic threshold level with the minimum the occupying area and the minimum charge/discharge power, by installing the resistance means in series to the source- drain line of at least one of p and n channel MISFET. CONSTITUTION:MISFETMN3, MP3 consisting of the minimum patterns of n and p channels constitute an inverter having input In and output OUT. And MISFETMRP for resistance functions to lower beta of the P-channel side and conducts constantly to increase the beta ratio equivalently. Thus the logic threshold level is shifted toward p channel. The beta ratio is controlled by the conductance of FETMRP. As a result, the driving FET can be made into the minimum pattern to obtain the multi-input circuit easily. In addition, the rotational design is possible in the smaller occupying area than conventional.

Inventors

  • 👤 Tsutomu Iima

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 11:28
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0021; H03K19/0027; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521

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